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參數(shù)資料
| 型號： | GS9064 |
| 元件分類： | 通信、網(wǎng)絡(luò)模塊及開發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁數(shù)： | 10/47頁 |
| 文件大?。?/td> | 754K |
| 代理商： | GS9064 |
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GENNUM CORPORATION
22208 - 0
10 of 47
G
35
V
Synchronous
with PCLK
Output
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the portion of the video field / frame that is used for
vertical blanking.
The V signal will be HIGH for the entire vertical blanking period as
indicated by the V bit in the received TRS signals.
The V signal will be LOW for all lines outside of the vertical blanking
interval.
36
H
Synchronous
with PCLK
Output
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the portion of the video line containing active video data.
H signal timing is configurable via the H_CONFIG bit of the
IOPROC_DISABLE register accessible via the host interface.
Active Line Blanking (H_CONFIG = 0
h
)
The H signal will be HIGH for the entire horizontal blanking period,
including the EAV and SAV TRS words, and LOW otherwise. This is the
default setting.
TRS Based Blanking (H_CONFIG = 1
h
)
The H signal will be HIGH for the entire horizontal blanking period as
indicated by the H bit in the received TRS ID words, and LOW otherwise.
37, 64
CORE_VDD
-
Power
Power supply connection for the digital core logic. Connect to +1.8V DC
digital.
38, 39,
42–48, 50
DOUT[0:9]
Synchronous
with PCLK
Output
PARALLEL DATA BUS
Signal levels are LVCMOS/LVTTL compatible.
DOUT9 is the MSB and DOUT0 is the LSB.
20-bit mode
20bit/10bit = HIGH
Chroma data output in SMPTE mode
SMPTE_BYPASS
= HIGH
DVB_ASI = LOW
Data output in Data-Through mode
SMPTE_BYPASS
= LOW
DVB_ASI = LOW
Forced LOW in DVB-ASI mode
SMPTE_BYPASS
= LOW
DVB_ASI = HIGH
10-bit mode
20bit/10bit = LOW
Forced LOW in all modes.
40, 49, 60
IO_GND
-
Power
Ground connection for digital I/O buffers. Connect to digital GND.
41, 53, 61
IO_VDD
-
Power
Power supply connection for digital I/O buffers. Connect to +3.3V DC
digital.
1.2 PIN DESCRIPTIONS (CONTINUED)
PIN
NUMBER
NAME
TIMING
TYPE
DESCRIPTION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GSA1 | Fuse |
| GSA1.25 | Fuse |
| GSA1.6 | Fuse |
| GSA10 | Fuse |
| GSA750 | Fuse |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS9064A | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:GS9064A HD-LINX㈢ II Adaptive Cable Equalizer |
| GS9064ACKDE3 | 制造商:Semtech Corporation 功能描述:Adaptive Cable Equalizer. High-speed BiCMOS integrated circuit. 16-Pin SOIC 制造商:Semtech Corporation 功能描述:SD/ASI Adaptive Equalizer |
| GS9064ACTDE3 | 制造商:Semtech Corporation 功能描述:SD/ASI Adaptive Equalizer |
| GS9064-CKD | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
| GS9064-CKDE3 | 制造商:Gennum Corporation 功能描述:Cable Equalizer 16-Pin SOIC |
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