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參數(shù)資料
| 型號(hào)： | GS9064 |
| 元件分類： | 通信、網(wǎng)絡(luò)模塊及開發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁數(shù)： | 27/47頁 |
| 文件大?。?/td> | 754K |
| 代理商： | GS9064 |
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GENNUM CORPORATION
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27 of 47
G
3.7.4 HVF Timing Signal Generation
The GS9060 extracts critical timing parameters from either
the received TRS signals (FW_EN/DIS = LOW), or from the
internal flywheel-timing generator (FW_EN/DIS = HIGH).
Horizontal blanking period (H), vertical blanking period (V),
and even / odd field (F) timing are all extracted and
presented to the application layer via the H:V:F status
output pins.
The H signal timing is configurable via the H_CONFIG bit of
the internal IOPROC_DISABLE register as either active line
based blanking, or TRS based blanking, (see Section
3.10.6).
Active line based blanking is enabled when the H_CONFIG
bit is set LOW. In this mode, the H output is HIGH for the
entire horizontal blanking period, including the EAV and
SAV TRS words. This is the default H timing used by the
device.
When H_CONFIG is set HIGH, TRS based blanking is
enabled. In this case, the H output will be HIGH for the
entire horizontal blanking period as indicated by the H bit in
the received TRS ID words.
The timing of these signals is shown in Figure 9.
Figure 9 H, V, F Timing
H:V:F TIMING – 20-BIT OUTPUT MODE
PCLK
CHROMA DATA OUT
LUMA DATA OUT
H
000
3FF
XYZ
000
V
F
000
3FF
(XYZ
000
H:V:F TIMING – 10-BIT OUTPUT MODE
MULTIPLEXED
Y/Cr/Cb DATA OUT
PCLK
H
V
F
XYZ
000
000
3FF
XYZ
000
000
3FF
H SIGNAL TIMING:
H_CONFIG = LOW
H_CONFIG = HIGH
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