參數(shù)資料
型號(hào)： GS9060*
英文描述： 270Mb/s Reclocking Deserializer with EDH for SDI and DVB-ASI. 3.3/1.8V supply.
中文描述： 270Mb / s的空間數(shù)據(jù)基礎(chǔ)設(shè)施和DVB硬腦膜外血腫時(shí)鐘重計(jì)解串器，意大利航天局。 3.3/1.8V供應(yīng)。
文件頁(yè)數(shù)： 9/47頁(yè)
文件大?。?/td> 754K
GENNUM CORPORATION
22208 - 0
9 of 47
G
29
SDIN_TDI
Synchronous
with
SCLK_TCK
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Serial Data In / Test Data Input
Host Mode (JTAG/HOST = LOW)
SDIN_TDI operates as the host interface serial input, SDIN, used to write
address and configuration information to the internal registers of the
device.
JTAG Test Mode (JTAG/HOST = HIGH)
SDIN_TDI operates as the JTAG test data input, TDI.
30
SCLK_TCK
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Serial Data Clock / Test Clock.
Host Mode (JTAG/HOST = LOW)
SCLK_TCK operates as the host interface burst clock, SCLK. Command
and data read/write words are clocked into the device synchronously with
this clock.
JTAG Test Mode (JTAG/HOST = HIGH)
SCLK_TCK operates as the JTAG test clock, TCK.
31
DATA_ERROR
Synchronous
with PCLK
Output
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
The DATA_ERROR signal will be LOW when an error within the received
data stream has been detected by the device. This pin is a logical 'OR'ing
of all detectable errors listed in the internal ERROR_STATUS register.
Once an error is detected, DATA_ERROR will remain LOW until the start of
the next video frame / field, or until the ERROR_STATUS register is read via
the host interface.
The DATA_ERROR signal will be HIGH when the received data stream has
been detected without error.
NOTE:
It is possible to program which error conditions are monitored by
the device by setting appropriate bits of the ERROR_MASK register HIGH.
All error conditions are detected by default.
32
FIFO_LD
Synchronous
with PCLK
Output
CONTROL SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Used as a control signal for external FIFO(s).
Normally HIGH but will go LOW for one PCLK period at SAV.
33, 68
CORE_GND
-
Power
Ground connection for the digital core logic. Connect to digital GND.
34
F
Synchronous
with PCLK
Output
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the ODD / EVEN field of the video signal.
The F signal will be HIGH for the entire period of field 2 as indicated by the
F bit in the received TRS signals.
The F signal will be LOW for all lines in field 1 and for all lines in
progressive scan systems.
1.2 PIN DESCRIPTIONS (CONTINUED)
PIN
NUMBER
NAME
TIMING
TYPE
DESCRIPTION
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS9060-CF 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Gennum Corporation 功能描述:
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GS9062 制造商:MINDSPEED_TECH 功能描述:
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