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參數(shù)資料
| 型號： | GS9060* |
| 英文描述： | 270Mb/s Reclocking Deserializer with EDH for SDI and DVB-ASI. 3.3/1.8V supply. |
| 中文描述： | 270Mb / s的空間數(shù)據(jù)基礎(chǔ)設(shè)施和DVB硬腦膜外血腫時鐘重計解串器，意大利航天局。 3.3/1.8V供應(yīng)。 |
| 文件頁數(shù)： | 11/47頁 |
| 文件大?。?/td> | 754K |
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GENNUM CORPORATION
22208 - 0
11 of 47
G
51, 52,
54–59, 62,
63
DOUT[10:19]
Synchronous
with PCLK
Output
PARALLEL DATA BUS
Signal levels are LVCMOS/LVTTL compatible.
DOUT19 is the MSB and DOUT10 is the LSB.
20-bit mode
20bit/10bit = HIGH
Luma data output in SMPTE mode
SMPTE_BYPASS = HIGH
DVB_ASI = LOW
Data output in Data-Through mode
SMPTE_BYPASS = LOW
DVB_ASI = LOW
DVB-ASI data in DVB-ASI mode
SMPTE_BYPASS = LOW
DVB_ASI = HIGH
10-bit mode
20bit/10bit = LOW
Multiplexed Luma and Chroma data output
in SMPTE mode
SMPTE_BYPASS
= HIGH
DVB_ASI = LOW
Data input in data through mode
SMPTE_BYPASS
= LOW
DVB_ASI = LOW
DVB-ASI data in DVB-ASI mode
SMPTE_BYPASS
= LOW
DVB_ASI = HIGH
65
YANC
Synchronous
with PCLK
Output
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the presence of ancillary data in the video stream.
For 20-bit demultiplexed data (20bit/10bit = HIGH), the YANC signal will
be HIGH when VANC or HANC data is detected in the luma video stream
and LOW otherwise.
For 10-bit multiplexed data (20bit/10bit = LOW), the YANC signal will be
HIGH when VANC or HANC data is detected anywhere in the data stream
and LOW otherwise.
66
CANC
Synchronous
with PCLK
Output
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the presence of ancillary data in the video stream.
For 20-bit demultiplexed data (20bit/10bit = HIGH), the CANC signal will
be HIGH when VANC or HANC data is detected in the chroma video
stream and LOW otherwise.
For 10-bit multiplexed data (20bit/10bit = LOW), the CANC signal will be
HIGH when VANC or HANC data is detected anywhere in the data stream
and LOW otherwise.
67
FW_EN/DIS
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to enable or disable the noise immune flywheel of the device.
When set HIGH, the internal flywheel is enabled. This flywheel is used in
the extraction and generation of TRS timing signals, in automatic video
standards detection, and in manual switch line lock handling.
When set LOW, the internal flywheel is disabled and TRS correction and
insertion is unavailable.
1.2 PIN DESCRIPTIONS (CONTINUED)
PIN
NUMBER
NAME
TIMING
TYPE
DESCRIPTION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS9062* | 270Mb/s Serializer with EDH for SDI and DVB-ASI. 3.3/1.8V supply. |
| GS9064 | Telecomm/Datacomm |
| GSA1 | Fuse |
| GSA1.25 | Fuse |
| GSA1.6 | Fuse |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS9060-CF | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Gennum Corporation 功能描述: |
| GS9060-CFE3 | 制造商:Semtech Corporation 功能描述: 制造商:Semtech Corporation 功能描述:Receiver for SD-SDI & DVB-ASI |
| GS9062 | 制造商:MINDSPEED_TECH 功能描述: |
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