參數(shù)資料
型號: GS9060*
英文描述: 270Mb/s Reclocking Deserializer with EDH for SDI and DVB-ASI. 3.3/1.8V supply.
中文描述: 270Mb / s的空間數(shù)據(jù)基礎(chǔ)設(shè)施和DVB硬腦膜外血腫時(shí)鐘重計(jì)解串器,意大利航天局。 3.3/1.8V供應(yīng)。
文件頁數(shù): 22/47頁
文件大?。?/td> 754K
GENNUM CORPORATION
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3.3.1 External VCO
The GS9060 requires the external GO1525 Voltage
Controlled Oscillator as part of the reclocker's phase-locked
loop. This external VCO implementation was chosen to
ensure high quality reclocking.
Power for the external VCO is generated entirely by the
GS9060 from an integrated voltage regulator. The internal
regulator uses +3.3V DC supplied via the CP_VDD /
CP_GND pins to provide +2.5V DC on the VCO_VCC /
VCO_GND pins.
The control voltage to the VCO is output from the GS9060
on the LF pin and requires 4.7k
pull-up and pull-down
resistors to ensure correct operation.
The GO1525 produces a reference signal for the reclocker,
input on the VCO pin of the GS9060. Both LF and VCO
signals should be referenced to the supplied VCO_GND as
shown in the recommended application circuit of Section
4.1.
3.3.2 Loop Bandwidth
The loop bandwidth of the integrated reclocker is nominally
1.4MHz, but may be increased or decreased via the
LB_CONT pin. It is recommended that this pin be
connected to VCO_GND through 39.2k
to maximize the
input jitter tolerance of the device.
3.4 SERIAL DIGITAL LOOP-THROUGH OUTPUT
The GS9060 contains an integrated current mode
differential serial digital cable driver with automatic slew
rate control. When enabled, this serial digital output
provides an active loop-through of the input signal.
To enable the loop-through output, SDO_EN/DIS must be
set HIGH by the application layer. Setting the SDO_EN/DIS
signal LOW will cause the SDO and SDO output pins to
become high impedance, resulting in reduced device
power consumption.
With suitable external return loss matching circuitry, the
GS9060's loop-through outputs will provide a minimum
output return loss of -15dB at 270Mb/s.
The integrated cable driver uses a separate power supply
of +1.8V DC supplied via the CD_VDD and CD_GND pins.
3.4.1 Output Swing
Nominally, the voltage swing of the serial digital loop-
through output is 800mV
p-p
single-ended into a 75
load.
This is set externally by connecting the RSET pin to
CD_VDD through 281
.
The loop-through output swing may be decreased by
increasing the value of the RSET resistor. The relationship is
approximated by the curve shown in Figure 7.
Alternatively, the serial digital output can drive 800mVp-p
into a 50
load. Since the output swing is reduced by a
factor of approximately one third when the smaller load is
used, the RSET resistor must be 187
to obtain 800mVp-p.
Figure 7 Serial Digital Loop-Through Output Swing
3.4.2 Reclocker Bypass Control
The serial digital loop-through output may be either a
buffered version of the serial digital input signal, or a
reclocked version of that signal.
The application layer may choose the reclocked output by
setting RC_BYP to logic HIGH. If RC_BYP is set LOW, the
data stream will bypass the internal reclocker and the serial
digital output will be a buffered version of the input.
3.4.3 Serial Digital Output Mute
The GS9060 will automatically mute the serial digital loop-
through output when the internal carrier_detect signal
indicates an invalid serial input.
The loop-through output will also be muted when SDO/SDO
is selected as reclocked, (RC_BYP = HIGH), but the lock
detect block has failed to lock to the data stream, (LOCKED
= LOW).
Table 1 summarizes the possible states of the serial digital
loop-through output data stream.
TABLE 1 SERIAL DIGITAL LOOP-THROUGH OUTPUT STATUS
SDO
CD
LOCKED
RC_BYP
RECLOCKED
LOW
HIGH
HIGH
BUFFERED
LOW
X
LOW
MUTED
LOW
LOW
HIGH
MUTED
HIGH
LOW*
X
*NOTE: LOCKED = HIGH if and only if CD = LOW
300
400
500
600
700
800
900
1000
250
300
350
400
450
500
550
600
650
700
RSET(
)
V
200
75
load
50
load
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