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參數(shù)資料
| 型號： | GS9060* |
| 英文描述： | 270Mb/s Reclocking Deserializer with EDH for SDI and DVB-ASI. 3.3/1.8V supply. |
| 中文描述： | 270Mb / s的空間數(shù)據(jù)基礎(chǔ)設(shè)施和DVB硬腦膜外血腫時鐘重計解串器，意大利航天局。 3.3/1.8V供應(yīng)。 |
| 文件頁數(shù)： | 28/47頁 |
| 文件大?。?/td> | 754K |
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GENNUM CORPORATION
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3.8 DVB-ASI FUNCTIONALITY
The GS9060 is said to be in DVB-ASI mode once the device
has detected 32 consecutive DVB-ASI words without a
single word or disparity error being generated. The device
will remain in DVB-ASI mode until 32 consecutive DVB-ASI
word or disparity errors are detected, or until SMPTE TRS ID
words have been detected.
The lock detect block may also drop out of DVB-ASI mode
under the following conditions:
RESET_TRST is asserted LOW
CDx is HIGH
SMPTE_BYPASS is asserted HIGH
DVB_ASI is asserted LOW
K28.5 sync patterns in the received DVB-ASI data stream
will be detected by the device in either inverted or non-
inverted form.
The application layer must set SMPTE_BYPASS LOW and
DVB_ASI HIGH in order to enable DVB-ASI operation.
3.8.1 DVB-ASI 8b/10b Decoding and Word Alignment
After serial-to-parallel conversion, the internal 10-bit data
bus is fed to the DVB-ASI 8b/10b decode and word
alignment block. The function of this block is to word align
the data to the K28.5 sync characters, and 8b/10b decode
and bit-swap the data to achieve bit alignment with the data
outputs.
The extracted 8-bit data will be presented to DOUT[17:10],
bypassing all internal SMPTE mode data processing.
NOTE: When operating in DVB-ASI mode, DOUT[9:0] are
forced LOW.
3.8.2 Status Signal Outputs
In DVB-ASI mode, the DOUT19 and DOUT18 pins will be
configured as DVB-ASI status signals SYNCOUT and
WORDERR respectively.
SYNCOUT will be HIGH whenever a K28.5 sync character
is present on the output.
This output may be used to drive
the write enable signal of an external FIFO, thus providing a
means of removing the K28.5 sync characters from the data
stream. Parallel DVB-ASI data may then be clocked out of
the FIFO at some rate less than 27MHz. See Figure 10.
WORDERR will be high whenever the device has detected
an illegal code word.
Figure 10 DVB-ASI FIFO Implementation using the GS9060
3.9 DATA THROUGH MODE
The GS9060 may be configured by the application layer to
operate as a simple serial-to-parallel converter. In this
mode, the device presents data to the output data bus
without performing any decoding, descrambling or word-
alignment.
Data
SMPTE_BYPASS and DVB_ASI input pins are set LOW.
Under these conditions, the lock detection algorithm enters
PLL lock mode, (see Section 3.6), such that the device may
reclock data not conforming to SMPTE or DVB-ASI streams.
through
mode
is
enabled
only
when
the
3.10 ADDITIONAL PROCESSING FUNCTIONS
The GS9060 contains an additional data processing block
which is available in SMPTE mode only, (see Section 3.7).
3.10.1 FIFO Load Pulse
To aid in the application-specific implementation of auto-
phasing and line synchronization functions, the GS9060 will
generate a FIFO load pulse to reset line-based FIFO
storage.
The FIFO_LD output pin will normally be HIGH but will go
LOW for one PCLK period, thereby generating a FIFO write
reset signal.
The FIFO load pulse will be generated such that it is co-
timed to the SAV XYZ code word presented to the output
data bus. This ensures that the next PCLK cycle will
correspond to the first active sample of the video line.
Figure 11 shows the timing relationship between the
FIFO_LD signal and the output video data.
8
8
AOUT ~ HOUT
WORDERR
PCLK = 27MHz
SYNCOUT
DDI
DDI
CLK_IN
CLK_OUT
FIFO
READ_CLK
<27MHz
FE
FF
TS
WE
WORDERR
GS9060
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PDF描述 |
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| GS9062* | 270Mb/s Serializer with EDH for SDI and DVB-ASI. 3.3/1.8V supply. |
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| GSA1 | Fuse |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS9060-CF | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Gennum Corporation 功能描述: |
| GS9060-CFE3 | 制造商:Semtech Corporation 功能描述: 制造商:Semtech Corporation 功能描述:Receiver for SD-SDI & DVB-ASI |
| GS9062 | 制造商:MINDSPEED_TECH 功能描述: |
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