參數(shù)資料
型號: GS9060*
英文描述: 270Mb/s Reclocking Deserializer with EDH for SDI and DVB-ASI. 3.3/1.8V supply.
中文描述: 270Mb / s的空間數(shù)據(jù)基礎(chǔ)設(shè)施和DVB硬腦膜外血腫時鐘重計解串器,意大利航天局。 3.3/1.8V供應(yīng)。
文件頁數(shù): 15/47頁
文件大?。?/td> 754K
GENNUM CORPORATION
22208 - 0
15 of 47
G
2.3 AC ELECTRICAL CHARACTERISTICS
T
A
= 0°C to 70°C, unless otherwise shown
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TEST
LEVEL
NOTES
SYSTEM
Serial Digital Input Jitter
Tolerance
IJT
Nominal loop bandwidth
0.6
-
-
UI
1
1
Slave Mode Asynchronous
Lock Time
No data to SD
-
-
197
us
6,7
2
No data to DVB-ASI
-
-
68
Device Latency
SMPTE and Data-Through
modes
-
21
-
PCLK
6
-
DVB-ASI mode
-
11
-
Reset Pulse Width
t
reset
1
-
-
ms
7
6
SERIAL DIGITAL DIFFERENTIAL INPUT
Serial Input Data Rate
DR
DDI
-
270
-
Mb/s
1
-
Serial Digital Input Signal
Swing
V
DDI
Differential with internal
100
input termination
200
600
1000
mV
p-p
1
-
SERIAL DIGITAL OUTPUT
Serial Output Data Rate
DR
SDO
-
270
-
Mb/s
1
-
Serial Output Swing
V
SDO
RSET = 281
Load = 75
-
800
-
mVp-p
1
-
Serial Output RiseTime
20% ~ 80%
tr
SDO
ORL compensation using
recommended circuit
400
550
1500
ps
1
-
Serial Output Fall Time
20% ~ 80%
tf
SDO
ORL compensation using
recommended circuit
400
550
1500
ps
1
-
Serial Output Intrinsic Jitter
t
IJ
Pseudorandom and
pathological
-
270
350
ps
1
3
Serial Output Duty Cycle
Distortion
DCD
SDO
-
20
-
ps
1
4
PARALLEL OUTPUT
Parallel Clock Frequency
f
PCLK
13.5
-
27.0
MHz
1
Parallel Clock Duty Cycle
DC
PCLK
40
50
60
%
1
Output Data Hold Time
t
OH
19.5
-
-
ns
1
5
Output Data Delay Time
t
OD
-
-
22.8
ns
1
5
Output Data Rise/Fall Time
tr/tf
-
-
1.5
ns
3
5
相關(guān)PDF資料
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