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G
3.12.2 Data Read and Write Timing
Read and write mode timing for the GSPI interface is shown
in Figure 17 and Figure 18 respectively. The maximum
SCLK frequency allowed is 6.6MHz.
When writing to the registers via the GSPI, the MSB of the
data word may be presented to SDIN immediately following
the falling edge of the LSB of the command word. All SDIN
data is sampled on the rising edge of SCLK.
When reading from the registers via the GSPI, the MSB of
the data word will be available on SDOUT 12ns (t
5
in Figure
17) following the falling edge of the LSB of the command
word, and thus may be read by the host on the very next
rising edge of the clock. The remaining bits are clocked out
by the GS9060 on the negative edges of SCLK.
Figure 17 GSPI Read Mode Timing
Figure 18 GSPI Write Mode Timing
3.12.3 Configuration and Status Registers
Table 16 summarizes the GS9060's internal status and
configuration registers.
All of these registers are available to the host via the GSPI
and are all individually addressable.
Where status registers contain less than the full 16 bits of
information however, two or more registers may be
combined at a single logical address.
SDOUT
R/W
RSV
RSV
A0
A1
A2
A3
A4
A5
RSV
RSV
RSV
RSV
RSV
RSV
D15
D14
D13
D12
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D11
D10
SCLK
CS
SDIN
RSV
t
0
t
2
t
3
input data
setup time
duty
cycle
t
4
period
t
5
t
6
output data
hold time
R/W
RSV
RSV
A0
A1
A2
A3
A4
A5
RSV
RSV
RSV
RSV
RSV
RSV
D15
D14
D13
D12
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D11
D10
SCLK
CS
SDIN
RSV
t
0
t
2
t
3
input data
setup time
duty
cycle
t
4
period
TABLE 16 GS9060 INTERNAL REGISTERS
ADDRESS
REGISTER NAME
SEE SECTION
00h
IOPROC_DISABLE
01h
ERROR_STATUS
Section 3.10.5
03h
EDH_FLAG
Section 3.10.7
04h
VIDEO_STANDARD
Section 3.10.4
05h - 09h
ANC_TYPE
Section 3.10.2.1
0Ch - 0Dh
VIDEO_FORMAT
Section 3.10.3
0Eh - 11h
RASTER_STRUCTURE
Section 3.10.4
12h - 19h
EDH_CALC_RANGES
Section 3.10.5.2
1Ah
ERROR_MASK
Section 3.10.5