- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370391 > GS9060* 270Mb/s Reclocking Deserializer with EDH for SDI and DVB-ASI. 3.3/1.8V supply. PDF資料下載
參數(shù)資料
| 型號： | GS9060* |
| 英文描述： | 270Mb/s Reclocking Deserializer with EDH for SDI and DVB-ASI. 3.3/1.8V supply. |
| 中文描述： | 270Mb / s的空間數(shù)據(jù)基礎設施和DVB硬腦膜外血腫時鐘重計解串器，意大利航天局。 3.3/1.8V供應。 |
| 文件頁數(shù)： | 8/47頁 |
| 文件大?。?/td> | 754K |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁
GENNUM CORPORATION
22208 - 0
8 of 47
G
22
CD_GND
-
Power
Ground connection for the serial digital cable driver. Connect to analog
GND.
23, 24
SDO, SDO
Analog
Output
Serial digital loop-through output signal operating at 270Mb/s.
The slew rate of these outputs is automatically controlled to meet SMPTE
259M specifications.
25
RESET_TRST
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to reset the internal operating conditions to default settings and to
reset the JTAG test sequence.
Host Mode (JTAG/HOST = LOW)
When asserted LOW, all functional blocks will be set to default conditions
and all input and output signals become high
impedance, including the
serial digital outputs SDO and
SDO.
Must be set HIGH for normal device operation.
JTAG Test Mode (JTAG/HOST = HIGH)
When asserted LOW, all functional blocks will be set to default and the
JTAG test sequence will be held in reset.
When set HIGH, normal operation of the JTAG test sequence resumes.
26
JTAG/HOST
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to select JTAG Test Mode or Host Interface Mode.
When set HIGH, CS_TMS, SDOUT_TDO, SDI_TDI and SCLK_TCK are
configured for JTAG boundary scan testing.
When set LOW, CS_TMS, SDOUT_TDO, SDI_TDI and SCLK_TCK are
configured as GSPI pins for normal host interface operation.
27
CS_TMS
Synchronous
with
SCLK_TCK
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Chip Select / Test Mode Select
Host Mode (JTAG/HOST = LOW)
CS_TMS operates as the host interface chip select,
CS
,
and is active
LOW.
JTAG Test Mode (JTAG/HOST = HIGH)
CS_TMS operates as the JTAG test mode select, TMS, and is active HIGH.
28
SDOUT_TDO
Synchronous
with
SCLK_TCK
Output
CONTROL SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Serial Data Output / Test Data Output
Host Mode (JTAG/HOST = LOW)
SDOUT_TDO operates as the host interface serial output, SDOUT, used to
read status and configuration information from the internal registers of the
device.
JTAG Test Mode (JTAG/HOST = HIGH)
SDOUT_TDO operates as the JTAG test data output, TDO.
1.2 PIN DESCRIPTIONS (CONTINUED)
PIN
NUMBER
NAME
TIMING
TYPE
DESCRIPTION
相關PDF資料 |
PDF描述 |
|---|---|
| GS9062* | 270Mb/s Serializer with EDH for SDI and DVB-ASI. 3.3/1.8V supply. |
| GS9064 | Telecomm/Datacomm |
| GSA1 | Fuse |
| GSA1.25 | Fuse |
| GSA1.6 | Fuse |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| GS9060-CF | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Gennum Corporation 功能描述: |
| GS9060-CFE3 | 制造商:Semtech Corporation 功能描述: 制造商:Semtech Corporation 功能描述:Receiver for SD-SDI & DVB-ASI |
| GS9062 | 制造商:MINDSPEED_TECH 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。