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參數(shù)資料
| 型號： | GS9060* |
| 英文描述： | 270Mb/s Reclocking Deserializer with EDH for SDI and DVB-ASI. 3.3/1.8V supply. |
| 中文描述： | 270Mb / s的空間數(shù)據(jù)基礎(chǔ)設(shè)施和DVB硬腦膜外血腫時(shí)鐘重計(jì)解串器，意大利航天局。 3.3/1.8V供應(yīng)。 |
| 文件頁數(shù)： | 7/47頁 |
| 文件大?。?/td> | 754K |
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GENNUM CORPORATION
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13
IOPROC_EN/DIS
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to enable or disable I/O processing features.
When set HIGH, the following I/O processing features of the device are
enabled:
EDH CRC Error Correction
ANC Data Checksum Correction
TRS Error Correction
Illegal Code Remapping
To enable a subset of these features, keep IOPROC_EN/DIS HIGH and
disable the individual feature(s) in the IOPROC_DISABLE register
accesible via the host interface.
When set LOW, the I/O processing features of the device are disabled,
regardless of whether the features are enabled in the IOPROC_DISABLE
register.
14
CD2
Non
Synchronous
Input
STATUS SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the presence of a serial digital input signal. Normally
generated by a Gennum automatic cable equalizer.
When LOW, the serial digital input signal received at the DDI2 and DDI2
pins is considered valid.
When HIGH, the associated serial digital input signal is considered to be
invalid. In this case, the LOCKED signal is set LOW and all parallel outputs
are muted.
15,17
DDI_2, DDI_2
Analog
Input
Differential input pair for serial digital input 2.
16
TERM2
Analog
Input
Termination for serial digital input 2. AC couple to PDBUFF_GND.
18
SMPTE_BYPASS
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
When set HIGH in conjunction with DVB_ASI = LOW, the device will be
configured to operate in SMPTE mode. All I/O processing features may be
enabled in this mode.
When set LOW, the device will not support the descrambling, decoding or
word alignment of received SMPTE data. No I/O processing features will
be available.
19
RSET
Analog
Input
Used to set the serial digital loop-through output signal amplitude.
Connect to CD_VDD through 281
+/- 1% for 800mV
p-p
single-ended
output swing.
20
CD_VDD
-
Power
Power supply connection for the serial digital cable driver. Connect to
+1.8V DC analog.
21
SDO_EN/DIS
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to enable or disable the serial digital output loop-through stage.
When set LOW, the serial digital output signals SDO and SDO are
disabled and become high impedance.
When set HIGH, the serial digital output signals SDO and SDO are
enabled.
1.2 PIN DESCRIPTIONS (CONTINUED)
PIN
NUMBER
NAME
TIMING
TYPE
DESCRIPTION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS9062* | 270Mb/s Serializer with EDH for SDI and DVB-ASI. 3.3/1.8V supply. |
| GS9064 | Telecomm/Datacomm |
| GSA1 | Fuse |
| GSA1.25 | Fuse |
| GSA1.6 | Fuse |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS9060-CF | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Gennum Corporation 功能描述: |
| GS9060-CFE3 | 制造商:Semtech Corporation 功能描述: 制造商:Semtech Corporation 功能描述:Receiver for SD-SDI & DVB-ASI |
| GS9062 | 制造商:MINDSPEED_TECH 功能描述: |
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