參數(shù)資料
型號(hào)： GS9060*
英文描述： 270Mb/s Reclocking Deserializer with EDH for SDI and DVB-ASI. 3.3/1.8V supply.
中文描述： 270Mb / s的空間數(shù)據(jù)基礎(chǔ)設(shè)施和DVB硬腦膜外血腫時(shí)鐘重計(jì)解串器，意大利航天局。 3.3/1.8V供應(yīng)。
文件頁數(shù)： 37/47頁
文件大?。?/td> 754K
GENNUM CORPORATION
22208 - 0
37 of 47
G
3.10.5.3 Lock Error Detection
The LOCKED pin of the GS9060 indicates the lock status of
the reclocker and lock detect blocks of the device. Only
when the LOCKED pin is asserted HIGH has the device
correctly locked to the received data stream, (see Section
3.6).
The GS9060 will also indicate lock error to the host interface
when LOCKED = LOW by setting the LOCK_ERR bit in the
ERROR_STATUS register HIGH.
3.10.5.4 Ancillary Data Checksum Error Detection
The GS9060 will calculate checksums for all received
ancillary data and compare the calculated values to the
received checksum words. If a mismatch is detected, the
error is flagged in the CS_ERR bits of the ERROR_STATUS
register.
Although the GS9060 will calculate and compare checksum
values for all ancillary data types by default, the host
interface may program the device to check only certain
types of ancillary data checksums.
This is accomplished via the ANC_TYPE register as
described in Section 3.10.2.1.
3.10.5.5 TRS Error Detection
TRS errors flags are generated by the GS9060 when:
1. The received TRS timing does not correspond to the
internal flywheel timing; or
2. The received TRS hamming codes are incorrect.
Both 8-bit and 10-bit SAV and EAV TRS words are checked
for timing and data integrity errors. These are flagged via
the SAV_ERR and/or EAV_ERR bits of the ERROR_STATUS
register.
Timing-based TRS errors will only be generated if the
FW_EN/DIS pin is set HIGH.
3.10.6 Error Correction and Insertion
In addition to signal error detection and indication, the
GS9060 may also correct certain types of errors by
inserting corrected code words and checksums into the
data stream. These features are only available in SMPTE
mode and IOPROC_EN/DIS must be set HIGH. Individual
correction features may be enabled or disabled via the
IOPROC_DISABLE register (Table 13).
All of the IOPROC_DISABLE register bits default to '0' after
device reset, enabling all of the processing features. To
disable any individual error correction feature, the host
interface must set the corresponding bit HIGH in the
IOPROC_DISABLE register.
TABLE 13 HOST INTERFACE DESCRIPTION FOR INTERNAL PROCESSING DISABLE REGISTER
REGISTER NAME
BIT
BIT NAME
DESCRIPTION
R/W
DEFAULT
IOPROC_DISABLE
Address: 00h
15-9
Not Used
8
H_CONFIG
Horizontal sync timing output configuration. Set LOW for
active line blanking timing. Set HIGH for H blanking
based on the H bit setting of the TRS words. See Figure
9.
0
7
Not Used
6
Not Used
5
ILLEGAL_REMAP
Illegal Code re-mapping. Correction of illegal code
words within the active picture. Set HIGH to disable. The
IOPROC_EN/DIS pin must be set HIGH.
R/W
0
4
EDH_CRC_INS
Error Detection & Handling (EDH) Cyclical Redundancy
Check (CRC) error correction insertion. Set HIGH to
disable. The IOPROC_EN/DIS pin must be set HIGH.
R/W
0
3
ANC_CSUM_INS
Ancillary Data Check-sum insertion. Set HIGH to
disable. The IOPROC_EN/DIS pin must be set HIGH.
R/W
0
2-1
Not Used
0
TRS_INS
Timing Reference Signal Insertion. Set HIGH to disable.
The IOPROC_EN/DIS pin must be set HIGH.
R/W
0
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