參數(shù)資料
型號: GS8342Q08AE-278
廠商: GSI TECHNOLOGY
元件分類: SRAM
英文描述: 4M X 8 DDR SRAM, 0.45 ns, PBGA165
封裝: 15 X 17 MM, 1 MM PITCH, FPBGA-165
文件頁數(shù): 22/35頁
文件大?。?/td> 1045K
代理商: GS8342Q08AE-278
GS8342Q08/09/18/36AE-278/250/200/167
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.06a 7/2008
29/35
2006, GSI Technology
SAMPLE/
PRELOAD
100
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
1
GSI
101
GSI private instruction.
1
RFU
110
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
1
BYPASS
111
Places Bypass Register between TDI and TDO.
1
Notes:
1. Instruction codes expressed in binary, MSB on left, LSB on right.
2. Default instruction automatically loaded at power-up and in test-logic-reset state.
JTAG Port Recommended Operating Conditions and DC Characteristics
Parameter
Symbol
Min.
Max.
Unit Notes
Test Port Input Low Voltage
VILJ
–0.3
0.3 * VDD
V
1
Test Port Input High Voltage
VIHJ
0.6 * VDD
VDD +0.3
V
1
TMS, TCK and TDI Input Leakage Current
IINHJ
–300
1
uA
2
TMS, TCK and TDI Input Leakage Current
IINLJ
–1
100
uA
3
TDO Output Leakage Current
IOLJ
–1
1
uA
4
Test Port Output High Voltage
VOHJ
VDD – 200 mV
V
5, 6
Test Port Output Low Voltage
VOLJ
0.4
V
5, 7
Test Port Output CMOS High
VOHJC
VDD – 100 mV
V
5, 8
Test Port Output CMOS Low
VOLJC
100 mV
V
5, 9
Notes:
1. Input Under/overshoot voltage must be –1 V < Vi < VDDn +1 V not to exceed 2.9 V maximum, with a pulse width not to exceed 20% tTKC.
2. VILJ ≤ VIN ≤ VDDn
3. 0 V
≤ VIN ≤ VILJn
4. Output Disable, VOUT = 0 to VDDn
5. The TDO output driver is served by the VDD supply.
6. IOHJ = –2 mA
7. IOLJ = + 2 mA
8. IOHJC = –100 uA
9. IOLJC = +100 uA
JTAG TAP Instruction Set Summary
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