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參數(shù)資料
| 型號： | GS8342Q08AE-278 |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 4M X 8 DDR SRAM, 0.45 ns, PBGA165 |
| 封裝： | 15 X 17 MM, 1 MM PITCH, FPBGA-165 |
| 文件頁數(shù)： | 1/35頁 |
| 文件大?。?/td> | 1045K |
| 代理商： | GS8342Q08AE-278 |
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GS8342Q08/09/18/36AE-278/250/200/167
36Mb SigmaQuad-II
Burst of 2 SRAM
167 MHz–278 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
165-Bump BGA
Commercial Temp
Industrial Temp
Rev: 1.06a 7/2008
1/35
2006, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
Simultaneous Read and Write SigmaQuad Interface
JEDEC-standard pinout and package
Dual Double Data Rate interface
Byte Write (x36, x18, and x9) and Nybble Write (x8) function
Burst of 2 Read and Write
1.8 V +100/–100 mV core power supply
1.5 V or 1.8 V HSTL Interface
Pipelined read operation
Fully coherent read and write pipelines
ZQ pin for programmable output drive strength
IEEE 1149.1 JTAG-compliant Boundary Scan
165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package
RoHS-compliant 165-bump BGA package available
Pin-compatible with present 9Mb and 18Mb and future 72Mb
and 144Mb devices
SigmaQuad Family Overview
The GSQ8342Q08/09/18/36AE are built in compliance with
the SigmaQuad-II SRAM pinout standard for Separate I/O
synchronous SRAMs. They are 37,748,736-bit (36Mb)
SRAMs. The GSQ8342Q08/09/18/36AE SigmaQuad SRAMs
are just one element in a family of low power, low voltage
HSTL I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GSQ8342Q08/09/18/36AE SigmaQuad-II SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer. The device also allows the user to manipulate the
output register clock quasi independently with the C and C
clock inputs. C and C are also independent single-ended clock
inputs, not differential inputs. If the C clocks are tied high, the
K clocks are routed internally to fire the output registers
instead.
Because Separate I/O SigmaQuad-II B2 RAMs always transfer
data in two packets, A0 is internally set to 0 for the first read or
write transfer, and automatically incremented by 1 for the next
transfer. Because the LSB is tied off internally, the address
field of a SigmaQuad-II B2 RAM is always one address pin
less than the advertised index depth (e.g., the 2M x 18 has a
1024K addressable index).
Parameter Synopsis
-278
-250
-200
-167
tKHKH
3.6 ns
4.0 ns
5.0 ns
6.0 ns
tKHQV
0.45 ns
0.5 ns
165-Bump, 15 mm x 17 mm BGA
1 mm Bump Pitch, 11 x 15 Bump Array
Bottom View
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| GS8342Q09AE-250 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 36MBIT 4M X 9 0.45NS 165FPBGA - Trays |
| GS8342Q10BD-200 | 制造商:GSI Technology 功能描述:165 FBGA - Bulk |
| GS8342Q18AE-167 | 制造商:GSI 功能描述: 制造商:GSI Technology 功能描述: |
| GS8342Q18AE-167I | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 36MBIT 2MX18 0.5NS 165FPBGA - Trays |
| GS8342Q18AE-200 | 制造商:GSI Technology 功能描述:SRAM SYNC DUAL 1.8V 36MBIT 2MX18 0.45NS 165FPBGA - Trays |
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