參數(shù)資料
型號(hào): GS8161EV32BD-200
廠商: GSI TECHNOLOGY
元件分類: SRAM
英文描述: 512K X 32 CACHE SRAM, 6.5 ns, PBGA165
封裝: 13 X 15 MM, 1 MM PITCH, FBGA-165
文件頁(yè)數(shù): 9/34頁(yè)
文件大小: 864K
代理商: GS8161EV32BD-200
GS8161EV18B(T/D)/GS8161EV32B(D)/GS8161EV36B(T/D)
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 9/2004
17/34
2004, GSI Technology
AC Test Conditions
Parameter
Conditions
Input high level
VDD – 0.2 V
Input low level
0.2 V
Input slew rate
1 V/ns
Input reference level
VDD/2
Output reference level
VDDQ/2
Output load
Fig. 1
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Device is deselected as defined by the Truth Table.
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
IIL
VIN = 0 to VDD
–1 uA
1 uA
ZZ Input Current
IIN1
VDD ≥ VIN ≥ VIH
0 V
≤ VIN ≤ VIH
–1 uA
1 uA
100 uA
Input Current
IIN2
VDD ≥ VIN ≥ VIL
0 V
≤ VIN ≤ VIL
–100 uA
–1 uA
1 uA
Output Leakage Current
IOL
Output Disable, VOUT = 0 to VDD
–1 uA
1 uA
Output High Voltage
VOH1
IOH = –4 mA, VDDQ = 1.6 V
VDDQ – 0.4 V
Output Low Voltage
VOL1
IOL = 4 mA, VDD = 1.6 V
0.4 V
DQ
VDDQ/2
50
30pF*
Output Load 1
* Distributed Test Jig Capacitance
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