參數(shù)資料
型號(hào)： GS8161EV32BD-200
廠商： GSI TECHNOLOGY
元件分類(lèi)： SRAM
英文描述： 512K X 32 CACHE SRAM, 6.5 ns, PBGA165
封裝： 13 X 15 MM, 1 MM PITCH, FBGA-165
文件頁(yè)數(shù)： 1/34頁(yè)
文件大?。?/td> 864K
代理商： GS8161EV32BD-200
GS8161EV18B(T/D)/GS8161EV32B(D)/GS8161EV36B(T/D)
1M x 18, 512K x 36, 512K x 36
18Mb Sync Burst SRAMs
250 MHz–150 MHz
1.8 V VDD
1.8 V I/O
100-Pin TQFP & 165-Bump BGA
Commercial Temp
Industrial Temp
Preliminary
Rev: 1.00 9/2004
1/34
2004, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Features
FT pin for user-configurable flow through or pipeline
operation
Dual Cycle Deselect (DCD) operation
IEEE 1149.1 JTAG-compatible Boundary Scan
1.8 V +10%/–10% core power supply
1.8 V I/O supply
LBO pin for Linear or Interleaved Burst mode
Internal input resistors on mode pins allow floating mode pins
Default to Interleaved Pipeline mode
Byte Write (BW) and/or Global Write (GW) operation
Internal self-timed write cycle
Automatic power-down for portable applications
JEDEC-standard 100-lead TQFP package
Pb-Free 100-lead TQFP package available
Functional Description
Applications
The GS8161EV18B(T/D)/GS8161EV32B(D)/GS8161EV36B(T/D)
is a 18,874,368-bit high performance synchronous SRAM with a
2-bit burst address counter. Although of a type originally
developed for Level 2 Cache applications supporting high
performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main store to
networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV) and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the
user via the FT mode pin (Pin 14). Holding the FT mode pin low
places the RAM in Flow Through mode, causing output data to
bypass the Data Output Register. Holding FT high places the
RAM in Pipeline mode, activating the rising-edge-triggered Data
Output Register.
DCD Pipelined Reads
The GS8161EV18B(T/D)/GS8161EV32B(D)/GS8161EV36B(T/D)
is a DCD (Dual Cycle Deselect) pipelined synchronous SRAM.
SCD (Single Cycle Deselect) versions are also available. DCD
SRAMs pipeline disable commands to the same degree as read
commands. DCD RAMs hold the deselect command for one full
cycle and then begin turning off their outputs just after the second
rising edge of clock.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High)
of the ZZ signal, or by stopping the clock (CK). Memory data is
retained during Sleep mode.
Core and Interface Voltages
The GS8161EV18B(T/D)/GS8161EV32B(D)/GS8161EV36B(T/D)
operates on a 1.8 V power supply. All input are 1.8 V compatible.
Separate output power (VDDQ) pins are used to decouple output
noise from the internal circuits and are 1..8 V compatible.
Parameter Synopsis
-250
-200
-150
Unit
Pipeline
3-1-1-1
tKQ
tCycle
2.5
4.0
3.0
5.0
3.8
6.7
ns
Curr (x18)
Curr (x32/x36)
280
330
230
270
185
210
mA
Flow Through
2-1-1-1
tKQ
tCycle
5.5
6.5
7.5
ns
Curr (x18)
Curr (x32/x36)
210
240
185
205
170
190
mA
相關(guān)PDF資料
PDF描述
GS8161Z18DGD-200IVT 1M X 18 ZBT SRAM, 6.5 ns, PBGA165
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