參數(shù)資料
型號(hào)： GS8161EV32BD-200
廠商： GSI TECHNOLOGY
元件分類： SRAM
英文描述： 512K X 32 CACHE SRAM, 6.5 ns, PBGA165
封裝： 13 X 15 MM, 1 MM PITCH, FBGA-165
文件頁(yè)數(shù)： 2/34頁(yè)
文件大?。?/td> 864K
代理商： GS8161EV32BD-200
GS8161EV18B(T/D)/GS8161EV32B(D)/GS8161EV36B(T/D)
Preliminary
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 9/2004
10/34
2004, GSI Technology
Note:
There are pull-up devices on the FT pin and a pull-down device on the ZZ pin, so those input pins can be unconnected and the chip will operate
in the default states as specified in the above tables.
Burst Counter Sequences
BPR 1999.05.18
Mode Pin Functions
Mode Name
Pin
Name
State
Function
Burst Order Control
LBO
L
Linear Burst
H
Interleaved Burst
Output Register Control
FT
L
Flow Through
H or NC
Pipeline
Power Down Control
ZZ
L or NC
Active
H
Standby, IDD = ISB
Note:
The burst counter wraps to initial state on the 5th clock.
Note:
The burst counter wraps to initial state on the 5th clock.
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00011011
2nd address
01
10
11
00
3rd address
10
11
00
01
4th address
11000110
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
00011011
2nd address
01
00
11
10
3rd address
10110001
4th address
11100100
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