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參數(shù)資料
| 型號： | GS8161Z18DGD-200IVT |
| 廠商： | GSI TECHNOLOGY |
| 元件分類： | SRAM |
| 英文描述： | 1M X 18 ZBT SRAM, 6.5 ns, PBGA165 |
| 封裝： | ROHS COMPLIANT, FPBGA-165 |
| 文件頁數(shù)： | 1/35頁 |
| 文件大小： | 488K |
| 代理商： | GS8161Z18DGD-200IVT |
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Rev: 1.00 6/2011
1/35
2011, GSI Technology
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS8161ZxxD(GT/D)-xxxV
18Mb Pipelined and Flow Through
Synchronous NBT SRAM
333 MHz–150 MHz
1.8 V or 2.5 V VDD
1.8 V or 2.5 V I/O
100-Pin TQFP & 165-Bump BGA
Commercial Temp
Industrial Temp
Preliminary
Features
User-configurable Pipeline and Flow Through mode
NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization
Fully pin-compatible with both pipelined and flow through
NtRAM, NoBL and ZBT SRAMs
IEEE 1149.1 JTAG-compatible Boundary Scan
1.8 V or 2.5 V core power supply
1.8 V or 2.5 V I/O supply
LBO pin for Linear or Interleave Burst mode
Pin-compatible with 2Mb, 4Mb, 8Mb, 36Mb, 72Mb and
144Mb devices
Byte write operation (9-bit Bytes)
3 chip enable signals for easy depth expansion
ZZ pin for automatic power-down
JEDEC-standard 165-bump BGA package
RoHS-compliant 100-pin TQFP and BGA packages available
Functional Description
The GS8161ZxxD(GT/D)-xxxV is an 18Mbit Synchronous
Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL
or other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable, ZZ and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8161ZxxD(GT/D)-xxxV may be configured by the user
to operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS8161ZxxD(GT/D)-xxxV is implemented with GSI's
high performance CMOS technology and is available in
JEDEC-standard 165-bump FP-BGA package.
Parameter Synopsis
-333
-250
-200
-150
Unit
Pipeline
3-1-1-1
tKQ
tCycle
3.0
4.0
3.0
5.0
3.8
6.7
ns
Curr (x18)
Curr (x36)
TBD
mA
Flow
Through
2-1-1-1
tKQ
tCycle
5.0
5.5
6.5
7.5
ns
Curr (x18)
Curr (x36)
TBD
mA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS8161Z18DT-250IV | 1M X 18 ZBT SRAM, 5.5 ns, PQFP100 |
| GS8161Z18DT-200T | 1M X 18 ZBT SRAM, 6.5 ns, PQFP100 |
| GS816218 | 1M x 18, 512K x 36 18Mb S/DCD Sync Burst SRAMs |
| GS816236D-150IT | 512K X 36 CACHE SRAM, 7.5 ns, PBGA165 |
| GS816236B-133IT | 512K X 36 CACHE SRAM, 8.5 ns, PBGA119 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS8161Z18DGD-200V | 制造商:GSI Technology 功能描述:165 BGA - Bulk |
| GS8161Z18DGD-250 | 制造商:GSI Technology 功能描述:165 BGA - Bulk |
| GS8161Z18DGD-375 | 制造商:GSI Technology 功能描述:165 BGA - Bulk |
| GS8161Z18DGD-375I | 制造商:GSI Technology 功能描述:165 BGA - Bulk |
| GS8161Z18DGT-150 | 制造商:GSI Technology 功能描述:100 TQFP - Bulk |
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