參數(shù)資料
型號(hào)： GS8161Z18DGD-200IVT
廠商： GSI TECHNOLOGY
元件分類： SRAM
英文描述： 1M X 18 ZBT SRAM, 6.5 ns, PBGA165
封裝： ROHS COMPLIANT, FPBGA-165
文件頁(yè)數(shù)： 20/35頁(yè)
文件大?。?/td> 488K
代理商： GS8161Z18DGD-200IVT
GS8161ZxxD(GT/D)-xxxV
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.00 6/2011
27/35
2011, GSI Technology
Preliminary
JTAG Tap Controller State Diagram
Instruction Descriptions
BYPASS
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-
tate testing of other devices in the scan path.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is
loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and
I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and
are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because
the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents
while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will
not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the
TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP
operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to Shift-DR state then
places the boundary scan register between the TDI and TDO pins.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with
all logic 0s. The EXTEST command does not block or override the RAM’s input pins; therefore, the RAM’s internal state is
still determined by its input pins.
Select DR
Capture DR
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
Select IR
Capture IR
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
Test Logic Reset
Run Test Idle
0
1
0
1
0
1
0
1
0
1
0
1
10
0
1
11
1
相關(guān)PDF資料
PDF描述
GS8161Z18DT-250IV 1M X 18 ZBT SRAM, 5.5 ns, PQFP100
GS8161Z18DT-200T 1M X 18 ZBT SRAM, 6.5 ns, PQFP100
GS816218 1M x 18, 512K x 36 18Mb S/DCD Sync Burst SRAMs
GS816236D-150IT 512K X 36 CACHE SRAM, 7.5 ns, PBGA165
GS816236B-133IT 512K X 36 CACHE SRAM, 8.5 ns, PBGA119
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
GS8161Z18DGD-200V 制造商:GSI Technology 功能描述:165 BGA - Bulk
GS8161Z18DGD-250 制造商:GSI Technology 功能描述:165 BGA - Bulk
GS8161Z18DGD-375 制造商:GSI Technology 功能描述:165 BGA - Bulk
GS8161Z18DGD-375I 制造商:GSI Technology 功能描述:165 BGA - Bulk
GS8161Z18DGT-150 制造商:GSI Technology 功能描述:100 TQFP - Bulk
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