參數(shù)資料
型號(hào)： GCIXF440ACT
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 78/128頁
文件大小： 1262K
代理商： GCIXF440ACT
Intel
IXF1002 Dual Port Gigabit Ethernet Controller
78
Datasheet
6.2
GMII Port Interface
In the GMII mode (PORT_MODE<GPCS=0>), the IXF1002 implements the IEEE 802.3 Standard
GMII interface.
Table 11
describes the GMII port signal names as they refer to the appropriate
IEEE 802.3 signal names.
The GMII management signals (mdc and mdio) are common to both ports.
Table 11
describes the GMII port signals versus standard signals.
Table 11. GMII Port Signals versus Standard Signals
GMII Signals
IEEE 802.3
Signals
I/O
Purpose
tclk
—
I
This signal operates at 125 MHz, and is used as a
reference clock for the gtxclk_{i} output signals.
gtxclk_{i}
gtx_clk
O
125MHz clock which provides the timing reference for
the transfer of the ten{i}, terr{i}, and txd_{i} signals.
rclk_{i}
rx_clk
I
Receive clock, synchronizes all receive signals (dv{i},
rxd_{i}<7:0>, rerr{i}).
ten{i}
tx_en
O
Transmit enable, asserted by the MAC sublayer when
the first transmit preamble byte is driven over the
GMII. It remains asserted for the remainder of the
frame, up to the last CRC byte.
txd_{i}<7:0>
txd<7:0>
O
These lines provide transmit data, driving a byte on
each tclk cycle when ten{i} is asserted.
terr{i}
tx_err
O
Transmit error, asserted by the MAC layer to generate
a coding error on the byte currently being transferred
over txd_{i}<7:0>.
dv{i}
rx_dv
I
Receive data valid, asserted by the PHY layer when
the first received preamble byte is driven over the
GMII. It remains asserted for the remainder of the
frame, up to the last CRC byte.
rxd_{i}<7:0>
rxd<7:0>
I
These lines provide receive data, driving a byte on
each rclk_{i} cycle when dv{i} is asserted.
rerr{i}
rx_err
I
Receive error, asserted by the PHY layer to indicate
an error the MAC cannot detect. If asserted during
packet reception, indicates a coding error on the
frame currently being transferred on rxd_{i}<7:0>.
mdc
mdc
O
Management data clock, the mdio signal clock
reference.
mdio
mdio
I/O
Management data input/output, used to transfer
control signals between the PHY layer and the
manager entity. The IXF1002 is capable of initiating
control signal transfer between the IXF1002 and the
PHY devices.
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