參數(shù)資料
型號: GCIXF440ACT
英文描述: Controller Miscellaneous - Datasheet Reference
中文描述: 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù): 16/128頁
文件大?。?/td> 1262K
代理商: GCIXF440ACT
Intel
IXF1002 Dual Port Gigabit Ethernet Controller
16
Datasheet
ewrap_{i}
O
GMII mode: Not in use, should be connected to a pull up resistor.
GPCS mode: Enable Wrap.
When asserted, the PHY should loop the transmit serialized data to the receive
section. This pin is controlled by bit LPBK in the GMII management control
register (GMII_CTL).
GMII mode: Not in use, should be connected to a pull up resistor.
GPCS mode: Lock to reference.
When asserted, enables the PHY to lock its PLL to the 125 MHz reference clock.
This pin is controlled by bit LCKE in the PORT_MODE register.
GMII mode: Not in use, should be left unconnected.
GPCS mode: Enable comma detect.
When asserted, enables the PHY for comma detect and word resynchronization.
When deasserted, the PHY will keep current word alignment and will not try to
detect new commas.
GMII mode: Not in use, should be connected to a pull up resistor.
GPCS mode: Comma detect.
An indication from the PHY layer that the data contains a valid comma character.
GMII management clock.
This pin is output after reset. Should be connected to a pull-up resistor.
MDC can be used as a general purpose pin according to the GMII_MGNG_ACC
register.
The mdc pin drives 0 by default and its output enable is controlled by bit MDCEN
in register MII_MNG_ACC.
GMII management input/output serial data.
Should be connected to a pull up resistor.
MDIO can be used as a general purpose pin according to the GMII_MGNG_ACC
register.
lckref_l_{i}
O
encdet_{i}
O
comdet_{i}
I
mdc
I/O
mdio
I/O
JTAG Interface
tck
tms
tdi
tdo
I
I
I
O
JTAG clock. If this pin is not used, it must be connected to 0.
JTAG test mode. If this pin is not used, it must be connected to 1.
JTAG data serial input. If this pin is not used, it must be connected to 1.
JTAG data serial output.
Table 2. Signal Descriptions (Sheet 6 of 6)
Signal Name
I/O
Pin Description
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