參數(shù)資料
型號(hào)： GCIXF440ACT
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 43/128頁
文件大?。?/td> 1262K
代理商： GCIXF440ACT
Intel
IXF1002 Dual Port Gigabit Ethernet Controller
Datasheet
43
Bit Name
Bit #
Bit Description
MDIO
15
GMII data IO
In direct access mode (AMAM=0):
During mdio write access (RWGMI=1), the value written to this bit is driven onto the
mdio signal.
During mdio read access (RWGMI=0), the mdio signal value is latched into this bit.
In automatic access mode (AMAM=1):
This bit is not valid.
MDC
14
MDC clock value
In direct access mode (AMAM=0):
During mdc write access (MDCEN=1), the value written to this bit is driven onto the
mdc signal. When access to the PHY is done using this bit, each new value must
remain stable for at least 200 ns.
During mdc read access (MDCEN=0), the mdc signal value is latched into this bit.
In automatic access mode (AMAM=1):
This bit is not valid
MDCEN
13
Enable MDC output
In direct access mode (AMAM=0):
When set enables mdc output.
In automatic access mode (AMAM=1):
This bit is not valid.
RWGMI
12
Read/write GMII management registers.
In direct access mode (AMAM=0):
When set enables mdio output.
In automatic access mode (AMAM=1):
Set this bit for writing the data from the GMII_MNG_DAT register into the GMII
management desired register.
Reset this bit for reading the GMII management desired register into the
GMII_MNG_DAT register.
PHY_ADD
11:7
GMII PHY address.
The address of the desired PHY. Bit 11 is the most significant bit and is the first PHY
address bit to be transmitted and received.
REG_ADD
6:2
GMII register address.
The address of the desired register. Bit 6 is the most significant bit and is the first register
address bit to be transmitted and received.
A4985-02
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
G
M
I
M
D
C
E
N
M
D
C
M
D
I
O
PHY_ADD
REG_ADD
G
M
I
R
Y
A
M
A
M
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