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參數(shù)資料
| 型號(hào)： | GCIXF440ACT |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 15/128頁(yè) |
| 文件大?。?/td> | 1262K |
| 代理商： | GCIXF440ACT |
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Intel
IXF1002 Dual Port Gigabit Ethernet Controller
Datasheet
15
txrdy_{i}
O
Transmit FIFO ready.
Indicates whether there is enough available space in the transmit FIFO to load
data according to the programmable threshold value. Following transmission
stop due to an error, the txrdy signal remains deasserted until the transmit error
status is read.
Receive FIFO ready.
Indicates whether there is enough available data in the receive FIFO to be stored
according to the programmable threshold value or if the end of the transferred
packet is in the FIFO. The rxrdy signal may also be programmed to assert when
the packet header is in the FIFO. rxrdy can also be asserted to report packet
discard from the receive FIFO due to an error together with the rxfail signal.
rxrdy_{i}
O
GMII / GPCS Interface
NOTE:
The following pins have various functions according to the port mode: GMII or GPCS. For a detailed
description, turn to
Section 6.0
.
tclk
I
125 MHz clock for reference.
GMII mode: 125 MHz Transmit clock.
GPCS mode: 125 MHz Transmit clock.
GMII mode: Byte transmit data.
GPCS mode: Eight low bits of the encoded transmit data.
GMII mode: Transmit enable signal.
GPCS mode: The ninth bit of the encoded transmit data.
GMII mode: Transmit error signal.
GPCS mode: The tenth bit of the encoded transmit data.
GMII mode: Receive recovered 125 MHz clock.
GPCS mode: The 62.5 MHz recovered receive byte clock. Used to latch odd
numbered bytes of the receive data.
GMII mode: Not in use, should be connected to a pull up resistor.
GPCS mode: The 62.5 MHz recovered receive byte clock. Used to latch even
numbered bytes of the receive data.
GMII mode: Byte receive data.
GPCS mode: Eight low bits of the encoded received data.
GMII mode: Receive enable signal.
GPCS mode: The ninth bit of the encoded received data.
GMII mode: Receive error signal.
GPCS mode: The tenth bit of the encoded received data.
GMII mode: Not in use, should be connected to a pull up resistor.
GPCS mode: Signal detect. Indicates whether the PHY has detected an input
signal at the serial input. If this signal is not driven into the IXF1002,
PORT_MODE<SDDIS> bit should be set.
GMII mode: Not in use, should be connected to a pull up resistor.
GPCS mode: Link indication.
When asserted, indicates link up. Meaning the synchronization process and the
Auto-Negotiation process were completed and the device is ready to transmit or
receive data.
GMII mode: Not in use, should be connected to a pull up resistor.
GPCS mode: Activity indication.
When asserted, indicates that data is being transmitted or received.
gtxclk_{i}/pmatclk_{i}
O
txd_{i}<7:0>
O
ten{i}/txd{i}<8>
O
terr{i}/txd{i}<9>
O
rclk_{i}
I
pmarclk_{i}
I
rxd_{i}<7:0>
I
dv{i}/rxd{i}<8>
I
rerr{i}/rxd{i}<9>
I
sd_{i}
I
lnk_{i}
O
act_{i}
O
Table 2. Signal Descriptions (Sheet 5 of 6)
Signal Name
I/O
Pin Description
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