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參數(shù)資料
| 型號： | GCIXF440ACT |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 62/128頁 |
| 文件大小： | 1262K |
| 代理商： | GCIXF440ACT |
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Intel
IXF1002 Dual Port Gigabit Ethernet Controller
62
Datasheet
4.1.3
FIFO Status Signaling
The IXF1002 reports the status of each FIFO through dedicated signals. Each transmit FIFO has a
txrdy signal indicating that there is enough free space to load new data. Each receive FIFO has a
rxrdy signal indicating that there is enough data to be transferred onto the IX Bus. The txrdy signals
are driven by the IXF1002 only when the txctl_l signal is asserted. The rxrdy signals are enabled by
the rxclt_l signal.The txrdy signal of a specific port is deasserted when the txsel_l signal is asserted
and the specific port is selected (fps). The same applies for the rxrdy signal of a specific port,
which is deasserted with rxsel_l assertion and the specific port selection (fps).
4.2
Packet Transmission
The following sections describe the packet transmission policy.
Note:
The signal naming below refers to the Full-64 IX Bus mode. Signal names should be changed in
accordance to the bus mode as described in
Section 4.1.1.1
and
Section 4.1.1.2
.
4.2.1
Packet Loading
The IXF1002 loads packets from the IX Bus into the transmit FIFO during burst accesses. In order
to guarantee a minimal amount of data transfer, the transmit FIFO txrdy signal reports minimal
space availability according to a programmable threshold (FFO_TSHD<TTH>).
When a new packet is loaded on the FIFO, the first cycle of the first burst must be signalled with
sop signal assertion. If TX_RX_PARAM<CRCD> is set or if the txasis signal is asserted together
with the sop signal, the packet will be sent onto the network without padding or CRC addition. In
this case, it is assumed by the IXF1002 that the CRC is valid and it will not be checked.
At the end of a packet load, the last data must be signalled with the assertion of the eop signal in the
last cycle of the last burst. If the txerr signal is asserted together with eop, the GMII error signal terr
will be asserted or a symbol error will be generated (GPCS mode) in the last data byte of the packet
sent onto the network. The CRC will be damaged if it was requested to be appended by the
IXF1002.
Note:
In case of VLAN tag append, strip or replace, the frame check sequence (FCS) field will be
calculated by the IXF1002 (see
Section 4.2.2.1
).
The IXF1002 may be programmed to handle only a single packet at a time
(TX_RX_PARAM<SPM>).
Byte masking signals (fbe_l[7:0]) may be used to load selective bytes. They can be used during packet
transfer to load packet segments on byte boundaries and for loading the exact number of bytes at the
end of a packet. Valid bytes may start at any byte boundary, while all valid bytes, in a given cycle, need
to be contiguous.
For example, a packet may be built up from the following buffers, with each one being transferred
in a different burst:
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