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| 型號： | GCIXF440ACT |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 14/128頁 |
| 文件大小： | 1262K |
| 代理商： | GCIXF440ACT |
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Intel
IXF1002 Dual Port Gigabit Ethernet Controller
14
Datasheet
eop/eop_rxf
I/O
End of packet.
In full-64 mode and in narrow mode (eop
–
I/O):
When asserted during transmit, indicates that the final data in the packet is
written to the transmit FIFO. During receive, eop is asserted when the final
data of the packet is transferred from the receive FIFO to the IX Bus.
In split mode (eop_rxf
–
output):
During receive, eop_rxf is asserted when the final data of the packet is
transferred from the receive FIFO to the IX Bus. In the following FIFO
access cycle, the packet status is driven onto the bus (see
Section 4.3.1.1
).
End of packet.
In full-64 mode and in narrow mode:
This signal is not in use and should be connected to a pull up resistor.
In split mode:
During transmit, indicates that the final data in the packet is written to the
transmit FIFO.
VLAN tag.
When asserted during transmit before sop assertion, VLAN tag will be appended
to the transmitted packet. When asserted during transmit together with sop
assertion, VLAN tag will be stripped from the transmitted packet. When asserted
during transmit before and also together with sop assertion, VLAN tag will be
replaced. See
Section 4.2.2
for more details.
NOTE:
In case of VLAN tag append, strip or replace, the frame check sequence
(FCS) field will be calculated by the IXF1002 (see
Section 4.2.2.1
).
Transmit as is/Transmit error.
When asserted during transmit, upon transfer of the packet
’
s first data (together
with sop assertion), no padding and/or CRC is appended to the packet even if
the port was programmed to do so. When asserted upon transfer of the packet
’
s
final data (together with eop assertion), the packet is transmitted with a CRC
error (if the port is programmed to append CRC), and a GMII error or a symbol
error (GPCS mode).
Receive packet failure.
This signal is asserted if a packet was received with errors, had started to appear
on the IX Bus, and was discarded from the receive FIFO.
Receive abort.
This signal forces a received packet, that is currently being transferred to the IX
Bus, to be aborted and flushed from the receive FIFO. May be asserted only with
rxsel_l assertion. Any following packets loaded onto the receive FIFO are not
affected by rxabt assertion.
Flow control.
When asserted, a flow-control packet with the programmed pause time is
transmitted. Upon deassertion, a flow-control packet with time equal to 0 is sent
if programmed accordingly. For correct latch of flct pin in the chip - signal flct_{i}
should be valid until 1 cycle after flct_lat deassertion.
Flow control pin enable
When asserted the flct_{i} pin will be sampled by the IXF1002. When deasserted,
the IXF1002 will latch the value of the flct_{i} pin, ignoring subsequent changes
to the flct_{i} pin.
Transmit control enable.
When asserted, this pin enables the txrdy_{i} output drivers to report the transmit
FIFO status.
Receive control enable.
When asserted, this pin enables the rxrdy_{i} output drivers to report the receive
FIFO status.
eop_txf
I
vtg
I
txasis/txerr
I
rxfail
O
rxabt
I
flct_{i}
I
flct_lat
I
txctl_l
I
rxctl_l
I
Table 2. Signal Descriptions (Sheet 4 of 6)
Signal Name
I/O
Pin Description
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