參數(shù)資料
型號: FW323
英文描述: 1394A PCI PHY/Link Open Host Controller Interface
中文描述: 1394A端口物理層的PCI /鏈接開放主機控制器接口
文件頁數(shù): 91/152頁
文件大?。?/td> 1625K
代理商: FW323
Agere Systems Inc.
91
Data Sheet, Rev. 2
October 2001
FW323 05
1394A PCI PHY/Link Open Host Controller Interface
Internal Registers
(continued)
Isochronous Transmit Interrupt Event Register
The isochronous transmit interrupt event set/clear register reflects the interrupt state of the isochronous transmit
contexts. An interrupt is generated on behalf of an isochronous transmit context if an OUTPUT_LAST command
completes and its interrupt bits are set. Upon determining that the interrupt event register isochTx (bit 6) interrupt
has occurred, software can check this register to determine which context(s) caused the interrupt. The interrupt
bits are set by an asserting edge of the corresponding interrupt signal, or by writing a 1 in the corresponding bit in
the set register. The only mechanism to clear the bits in this register is to write a 1 to the corresponding bit in the
clear register.
Table 78. Isochronous Transmit Interrupt Event Register
Bit
Field
Name
Reserved
Type
Default
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
isoXmit7
isoXmit6
isoXmit5
isoXmit4
isoXmit3
isoXmit2
isoXmi1t
isoXmit0
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
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