參數(shù)資料
型號： FW323
英文描述： 1394A PCI PHY/Link Open Host Controller Interface
中文描述： 1394A端口物理層的PCI /鏈接開放主機控制器接口
文件頁數(shù)： 16/152頁
文件大?。?/td> 1625K
代理商： FW323
16
Agere Systems Inc.
FW323 05
1394A PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 2
October 2001
Pin Information
(continued)
Table 1. Pin Descriptions
(continued)
Pin
79
80
81
82
83
84
85
86
Symbol*
PCI_AD[3]
PCI_AD[2]
V
SS
V
DD
PCI_AD[1]
PCI_AD[0]
PCI_VIOS
CONTENDER
* Active-low signals within this document are indicated by an N following the symbol names.
Type
I/O
I/O
—
—
I/O
I/O
—
I
Description
PCI Address/Data Bit.
PCI Address/Data Bit.
Ground.
Power.
PCI Address/Data Bit.
PCI Address/Data Bit.
PCI Signaling Indicator.
(5 V or 3.3 V.)
Contender.
On hardware reset, this input sets the
default value of the CONTENDER bit indicated during
self-ID. This bit can be programmed by tying the signal
to V
DD
(high) or to ground (low).
Power-Class Indicators.
On hardware reset, these
inputs set the default value of the power class indicated
during self-ID. These bits can be programmed by tying
the signals to V
DD
(high) or to ground (low).
Link On.
Signal from the internal PHY core to the
internal link core. This signal is provided as an output
for use in legacy power management systems.
Link Power Status.
Signal from the internal link core to
the internal PHY core. LPS is provided as an output for
use in legacy power management systems.
No Connect.
Power.
Cable Power Status.
CPS is normally connected to the
cable power through a 400 k
resistor. This circuit
drives an internal comparator that detects the presence
of cable power. This information is maintained in one
internal register and is available to the LLC by way of a
register read (see IEEE 1394a-2000, Standard for a
High Performance Serial Bus (Supplement)).
Analog Circuit Ground.
All V
SSA
signals should be
tied together to a low-impedance ground plane.
Analog Circuit Power.
V
DDA
supplies power to the
analog portion of the device.
Port 2, Port Cable Pair B.
TPB2± is the port B connec-
tion to the twisted-pair cable. Board traces from each
pair of positive and negative differential signal pins
should be kept matched and as short as possible to the
external load resistors and to the cable connector.
Port 2, Port Cable Pair A.
TPA2± is the port A connec-
tion to the twisted-pair cable. Board traces from each
pair of positive and negative differential signal pins
should be kept matched and as short as possible to the
external load resistors and to the cable connector.
87
88
89
PC2
PC1
PC0
I
90
LKON
O
91
LPS
O
92
93
94
NC
V
DD
CPS
—
—
I
95
V
SSA
—
96
V
DDA
—
97
TPB2-
Analog I/O
98
TPB2+
99
TPA2-
Analog I/O
100
TPA2+
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