參數(shù)資料
型號(hào): FW323
英文描述: 1394A PCI PHY/Link Open Host Controller Interface
中文描述: 1394A端口物理層的PCI /鏈接開放主機(jī)控制器接口
文件頁數(shù): 27/152頁
文件大?。?/td> 1625K
代理商: FW323
Agere Systems Inc.
27
Data Sheet, Rev. 2
October 2001
FW323 05
1394A PCI PHY/Link Open Host Controller Interface
Internal Registers
(continued)
Table 10. Class Code and Revision ID Register Description
Latency Timer and Class Cache Line Size Register
The latency timer and class cache line size register is programmed by host BIOS to indicate system cache line
size and the latency timer associated with the FW323.
Table 11. Latency Timer and Class Cache Line Size Register
Register:
Type:
Offset:
Default:
Latency timer and class cache line size register
Read/write
0Ch
0000h
Bit
31:24
Field Name
BASECLASS
Type
R
Description
Base Class.
This field returns 0Ch when read, which classifies the func-
tion as a serial bus controller.
Subclass.
This field returns 00h when read, which specifically classifies
the function as an IEEE 1394 serial bus controller.
Programming Interface.
This field returns 10h when read, indicating
that the programming model is compliant with the 1394 Open Host
Controller Interface Specification
Silicon Revision.
This field returns 04h when read, indicating the silicon
revision of the FW323.
23:16
SUBCLASS
R
15:8
PGMIF
R
7:0
CHIPREV
R
Bit
Field
Name
Type
Default
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LATENCY_TIMER
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CACHELINE_SZ
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