參數(shù)資料
型號(hào)： FW323
英文描述： 1394A PCI PHY/Link Open Host Controller Interface
中文描述： 1394A端口物理層的PCI /鏈接開(kāi)放主機(jī)控制器接口
文件頁(yè)數(shù)： 7/152頁(yè)
文件大?。?/td> 1625K
代理商： FW323
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Agere Systems Inc.
7
Data Sheet, Rev. 2
October 2001
FW323 05
1394A PCI PHY/Link Open Host Controller Interface
FW323 Functional Overview
I
PCI:
— Revision 2.2 compliant
— 33 MHz/32-bit operation
— Programmable burst size for PCI data transfer
— Supports PCI Bus Power Management Interface Specification v.1.1
— Supports clockrun protocol per PCI Mobile Design Guide
— Global byte swap function
Other Features
I
I
2
C serial ROM interface
I
CMOS process
I
3.3 V operation, 5 V tolerant inputs
I
128-pin TQFP package
The FW323 is the Agere Systems Inc. implementation of a high-performance, PCI bus-based open host controller for
implementation of IEEE 1394a-2000 compliant systems and devices. Link-layer functions are handled by the
FW323, utilizing the on-chip 1394a-2000 compliant link core and physical layer core. A high-performance and cost-
effective solution for connecting and servicing multiple IEEE 1394 (both 1394-1995 and 1394a-2000) peripheral
devices can be realized.
5-6250 (F).e
Figure 1. FW323 Functional Block Diagram
PCI
BUS
CABLE PORT 2
PCI
CORE
ROM
OHCI
ISOCH
OHCI
ASYNC
LINK
CORE
I/F
PHY
CORE
CABLE PORT 1
CABLE PORT 0
FW323 Functional Description
The FW323 is comprised of five major functional
sections (see Figure 1): PCI core, isochronous data
transfer, asynchronous data transfer, link core, and
PHY core. The following is a general description of
each of the five major sections.
PCI Core
The PCI core serves as the interface to the PCI bus. It
contains the state machines that allow the FW323 to
respond properly when it is the target of the transaction.
During 1394 packet transmission or reception, the PCI
core arbitrates for the PCI bus and enables the FW323
to become the bus master for reading the different
buffer descriptors and management of the actual data
transfers to/from host system memory.
The PCI core also supports the PCI Bus Power
Management Interface Specification v.1.1. Included in
this support is a standard power management register
interface accessible through the PCI configuration
space. Through this register interface, software is able
to transition the FW323 into four distinct power
consumption states (D0, D1, D2, and D3). This permits
software to selectively increase/decrease the power
consumption of the FW323 for reasons such as periods
of system inactivity or power conservation. In addition,
the FW323 also includes support for hardware wake-up
mechanisms through power management events
相關(guān)PDF資料
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參數(shù)描述
FW32305 制造商:AGERE 制造商全稱:AGERE 功能描述:1394A PCI PHY/Link Open Host Controller Interface
FW32306 制造商:AGERE 制造商全稱:AGERE 功能描述:PCI PHY/Link Open Host Controller Interface
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FW323061394A 制造商:AGERE 制造商全稱:AGERE 功能描述:PCI PHY/Link Open Host Controller Interface
FW-33-01-G-D-200-065 制造商:Samtec Inc 功能描述:CONN BD STACKER HDR 66 POS 1.27MM SLDR ST TH - Bulk
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