參數(shù)資料
型號(hào)： FW323
英文描述： 1394A PCI PHY/Link Open Host Controller Interface
中文描述： 1394A端口物理層的PCI /鏈接開放主機(jī)控制器接口
文件頁數(shù)： 87/152頁
文件大小： 1625K
代理商： FW323
Agere Systems Inc.
87
Data Sheet, Rev. 2
October 2001
FW323 05
1394A PCI PHY/Link Open Host Controller Interface
Internal Registers
(continued)
Register:
Type:
Offset:
Interrupt event register
Read/set/clear/update
80h
set register
84h
clear register (returns the content of the interrupt event and interrupt mask registers
when read)
XXXX 0XXXh
Default:
Table 75. Interrupt Event Register Description
Bit
31
30
Field Name
Reserved
vendorSpecific
Type
R
RSC
Description
Reserved.
Bit 31 returns 0 when read.
This vendor-specific interrupt event is reported when serial ROM
read is complete.
Reserved.
Bits 29:27 return 0s when read.
The FW323 has received a PHY core register data byte which can
be read from the PHY core layer control register.
If bit 21 (cycleMaster) of the link control register is set, then this
indicates that over 125 ms have elapsed between the start of
sending a cycle start packet and the end of a subaction gap. The
link control register bit 21 (cycleMaster) is cleared by this event.
This event occurs when the FW323 encounters any error that
forces it to stop operations on any or all of its subunits, for
example, when a DMA context sets its dead bit. While this bit is
set, all normal interrupts for the context(s) that caused this inter-
rupt are blocked from being set.
A cycle start was received that had values for cycleSeconds and
cycleCount fields that are different from the values in bits 31:25
(cycleSeconds field) and bits 24:12 (cycleCount field) of the isoch-
ronous cycle timer register.
A lost cycle is indicated when no cycle_start packet is sent/
received between two successive cycleSynch events. A lost cycle
can be predicted when a cycle_start packet does not immediately
follow the first subaction gap after the cycleSynch event or if an
arbitration reset gap is detected after a cycleSynch event without
an intervening cycle start. This bit may be set either when it occurs
or when logic predicts that it will occur.
Indicates that the seventh bit of the cycle second counter has
changed.
Indicates that a new isochronous cycle has started. This bit is set
when the low order bit of the cycle count toggles.
Indicates the PHY core requests an interrupt through a status
transfer.
Reserved.
Bit 18 returns 0 when read.
Indicates that the PHY core chip has entered bus reset mode.
A selfID Packet Stream Has Been Received.
It is generated at
the end of the bus initialization process. This bit is turned off simul-
taneously when bit 17 (busReset) is turned on.
29:27
26
Reserved
phyRegRcvd
R
RSCU
25
cycleTooLong
RSCU
24
unrecoverableError
RSCU
23
cycleInconsistent
RSCU
22
cycleLost
RSCU
21
cycle64Seconds
RSCU
20
cycleSynch
RSCU
19
PHY
RSCU
18
17
16
Reserved
busReset
selfIDcomplete
R
RSCU
RSCU
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