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參數(shù)資料
| 型號(hào)： | FW323 |
| 英文描述： | 1394A PCI PHY/Link Open Host Controller Interface |
| 中文描述： | 1394A端口物理層的PCI /鏈接開(kāi)放主機(jī)控制器接口 |
| 文件頁(yè)數(shù)： | 9/152頁(yè) |
| 文件大?。?/td> | 1625K |
| 代理商： | FW323 |
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Agere Systems Inc.
9
Data Sheet, Rev. 2
October 2001
FW323 05
1394A PCI PHY/Link Open Host Controller Interface
FW323 Functional Description
(continued)
Asynchronous Transmit (ASYNC_TX)
The ASYNC_TX block of the FW323 manages the
asynchronous transmission of either request or
response packets. The mechanism for asynchronous
transmission of requests and responses are similar.
The only difference is the system memory location of
the buffer descriptor list when processing the two
contexts. Therefore, the discussion below, which is for
asynchronous transmit requests, parallels that of the
asynchronous transmit response. The FW323 asyn-
chronous transmission of packets involves the following
steps:
1. Fetch complete buffer descriptor block from host
memory.
2. Get data from system memory and store into
async FIFO.
3. Request transfer of data from FIFO to link device.
4. Handle retries, if any.
5. Handle errors in steps 1 to 4.
6. End the transfer if there are no errors.
Asynchronous Receive (ASYNC_RX)
The ASYNC_RX block of the FW323 manages the
processing of received packets. Data packets are
parsed and stored in a dedicated asynchronous
receive FIFO. Command descriptors are read through
the PCI interface to determine the disposition of the
data arriving through the 1394 link.
The header of the received packet is processed to
determine, among other things, the following:
1. The type of packet received.
2. The source and destinations.
3. The data and size, if any.
4. The operation required, if any. For example, com-
pare and swap operation.
The ASYNC block also handles DMA transfers of self-
ID packets during the 1394 bus initialization phase and
block transactions associated with physical request.
Serial EEPROM Interface
The FW323 features an
I
2
C
compliant serial ROM
interface that allows for the connection of an external
serial EEPROM. The interface provides a mechanism
to store configuable data such as the global unique
identification (GUID) within an external EEPROM. The
interface consists of the ROM_AD and ROM_CLK pins.
ROM_CLK is an output clock provided by the FW323 to
the external EEPROM. ROM_AD is bidirectional and is
used for serial data/control transfer between the FW323
and the external EEPROM. The FW323 uses this
interface to read the contents of the serial EEPROM
during initial power-up or when a hardware reset
occurs. The FW323 also makes the serial ROM
interface visible to software through the OHCI defined
GUID ROM register. When the FW323 is operational,
the GUID ROM register allows software to initiate reads
to the external EEPROM.
Link Core
It is the responsibility of the link to ascertain if a
received packet is to be forwarded to the OHCI for
processing. If so, the packet is directed to a proper
inbound FIFO for either the isochronous block or the
asynchronous block to process. The link is also
responsible for CRC generation on outgoing packets
and CRC checking on receiving packets.
To become aware of data to be sent outbound on 1394
bus, the link must monitor the OHCI FIFOs looking for
packets in need of transmission. Based on data
received from the OHCI block, the link will form packet
headers for the 1394 bus. The link will alert the PHY
core as to the availability of the outbound data. It is the
link’s function to generate CRC for the outbound data.
The link also provides PHY core register access for the
OHCI.
PHY Core
The PHY core provides the analog physical layer func-
tions needed to implement a three-port node in a
cable-based IEEE 1394-1995 and IEEE 1394a-2000
network.
Each cable port incorporates two differential line trans-
ceivers. The transceivers include circuitry to monitor
the line conditions as needed for determining connec-
tion status, for initialization and arbitration, and for
packet reception and transmission. The PHY core
interfaces with the link core.
The PHY core requires either an external 24.576 MHz
crystal or crystal oscillator. The internal oscillator
drives an internal phase-locked loop (PLL), which gen-
erates the required 400 MHz reference signal. The
400 MHz reference signal is internally divided to pro-
vide the 49.152 MHz, 98.304 MHz, and 196.608 MHz
clock signals that control transmission of the outbound
clock signal is also supplied to the associated LLC for
synchronization of the two chips and is used for resyn-
chronization of the received data.
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相關(guān)代理商/技術(shù)參數(shù) |
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| FW32305 | 制造商:AGERE 制造商全稱:AGERE 功能描述:1394A PCI PHY/Link Open Host Controller Interface |
| FW32306 | 制造商:AGERE 制造商全稱:AGERE 功能描述:PCI PHY/Link Open Host Controller Interface |
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| FW323061394A | 制造商:AGERE 制造商全稱:AGERE 功能描述:PCI PHY/Link Open Host Controller Interface |
| FW-33-01-G-D-200-065 | 制造商:Samtec Inc 功能描述:CONN BD STACKER HDR 66 POS 1.27MM SLDR ST TH - Bulk |
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