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參數資料
| 型號： | FW323 |
| 英文描述： | 1394A PCI PHY/Link Open Host Controller Interface |
| 中文描述： | 1394A端口物理層的PCI /鏈接開放主機控制器接口 |
| 文件頁數： | 18/152頁 |
| 文件大小： | 1625K |
| 代理商： | FW323 |
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18
Agere Systems Inc.
FW323 05
1394A PCI PHY/Link Open Host Controller Interface
Data Sheet, Rev. 2
October 2001
Pin Information
(continued)
Table 1. Pin Descriptions
(continued)
Application Schematic
The application schematic presents a complete three-port, 400 Mbits/s IEEE 1394a-2000 design, featuring the
Agere FW323 PCI bus-based host OHCI controller and 400 Mbits/s PHY core. The FW323 device needs only a
power source (U3), connection to PCI interface, 1394a-2000 terminators and connectors, crystal, and serial
EEPROM. No external PHY is required because the FW323 contains both host controller and PHY core functions.
This design is a secondary (Class 4) power provider to the 1394 bus, and will participate in the required 1394a-
2000 bus activities, even when power on the PCI bus is not energized.
Pin
117
Symbol*
R0
* Active-low signals within this document are indicated by an N following the symbol names.
Type
I
Description
Current Setting Resistor.
An internal reference
voltage is applied to a resistor connected between R0
and R1 to set the operating current and the cable driver
output current. A low temperature-coefficient resistor
(TCR) with a value of 2.49 k
± 1% should be used to
meet the IEEE 1394-1995 standard requirements for
output voltage limits.
Power for PLL Circuit.
PLLV
DD
supplies power to the
PLL circuitry portion of the device.
Ground for PLL Circuit.
PLLV
SS
is tied to a low-
impedance ground plane.
Crystal Oscillator.
XI and XO connect to a
24.576 MHz parallel resonant fundamental mode
crystal. Although when a 24.576 MHz clock source is
used, it can be connected to XI with XO left uncon-
nected. The optimum values for the external shunt
capacitors are dependent on the specifications of the
crystal used. The suggested values of 12 pF are appro-
priate for crystal with 7 pF specified loads. For more
details, see the Crystal Selection Considerations
section.
Reset (Active-Low).
When RESETN is asserted low
(active), a bus reset condition is set on the active cable
ports and the internal PHY core logic is reset to the
reset start state. An internal pull-up resistor, which is
connected to V
DD
, is provided, so only an external
delay capacitor and resistor are required. This input is a
standard logic buffer and can also be driven by an
open-drain logic output buffer.
Test.
Used for device testing. Tie to V
SS
.
Test Mode Control.
SM is used during the manufac-
turing test and should be tied to V
SS
.
Test Mode Control.
SE is used during the manufac-
turing test and should be tied to V
SS
.
No Connect.
No Connect.
118
R1
119
PLLV
DD
—
120
PLLV
SS
—
121
XI
—
122
XO
123
RESETN
I
124
125
PTEST
SM
I
I
126
SE
I
127
128
NC
NC
—
—
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