參數(shù)資料
型號(hào)： EVAL-ADV739XFEZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 52/108頁(yè)
文件大小： 0K
描述： BOARD EVAL FOR ADV739XFEZ
標(biāo)準(zhǔn)包裝： 1
系列： Advantiv®
主要目的： 視頻，視頻處理
嵌入式： 否
已用 IC / 零件： ADV7403
主要屬性： NTSC/PAL 數(shù)字視頻解碼器
次要屬性： 前端板，用于 ADV7390、ADV7391、ADV7392 和 ADV7393 編碼器背端板
已供物品： 板
ADV7390/ADV7391/ADV7392/ADV7393
Data Sheet
Rev. G | Page 48 of 108
ENHANCED DEFINITION/HIGH DEFINITION
Subaddress 0x01, Bits[6:4] = 001 or 010
ED or HD YCrCb data can be input in a 4:2:2 format over an
8-/10-bit DDR bus or a 16-bit SDR bus.
The clock signal must be provided on the CLKIN pin. If
required, external synchronization signals can be provided on
the HSYNC and VSYNC pins. Embedded EAV/SAV timing
codes are also supported.
16-Bit 4:2:2 YCrCb Mode (SDR)
In 16-bit 4:2:2 YCrCb input mode, the Y pixel data is input on
Pin P15 to Pin P8, with P8 being the LSB.
The CrCb pixel data is input on Pin P7 to Pin P0, with Pin P0
being the LSB.
8-/10-Bit 4:2:2 YCrCb Mode (DDR)
In 8-/10-bit DDR 4:2:2 YCrCb input mode, the Y pixel data is
input on Pin P15 to Pin P8/P6 on either the rising or falling
edge of CLKIN. Pin P8/P6 is the LSB.
The CrCb pixel data is also input on Pin P15 to Pin P8/P6
on the opposite edge of CLKIN. P8/P6 is the LSB.
The 10-bit mode is enabled using Subaddress 0x33, Bit 2.
Whether the Y data is clocked in on the rising or falling edge of
CLKIN is determined by Subaddress 0x01, Bits[2:1] (see Figure 57
Figure 57. ED/HD-DDR Input Sequence (EAV/SAV)—Option A
Figure 58. ED/HD-DDR Input Sequence (EAV/SAV)—Option B
Figure 59. ED/HD-SDR Example Application
Figure 60. ED/HD-DDR Example Application
ENHANCED DEFINITION (AT 54 MHz)
Subaddress 0x01, Bits[6:4] = 111
ED YCrCb data can be input in an interleaved 4:2:2 format on
an 8-/10-bit bus at a rate of 54 MHz.
A 54 MHz clock signal must be provided on the CLKIN pin.
Embedded EAV/SAV timing codes are supported. External
synchronization signals are not supported in this mode.
The interleaved pixel data is input on Pin P15 to Pin P8/P6,
with Pin P8/P6 being the LSB.
The 10-bit mode is enabled using Subaddress 0x33, Bit 2.
Figure 61. ED (at 54 MHz) Input Sequence (EAV/SAV)
Figure 62 ED (at 54 MHz) Example Application
3FF
00
X
Y
Y0
Y1
Cr0
CLKIN
NOTES
1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 00 IN THIS CASE.
2. 10-BIT MODE IS ENABLED USING SUBADDRESS 0x33, BIT 2.
P[15:8]/
P]15:6]
Cb0
06234-
055
3FF
00
XY
Cb0
Cr0
Y1
CLKIN
P[15:8]/
P[15:P6]
Y0
NOTES
1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 11 IN THIS CASE.
2. 10-BIT MODE IS ENABLED USING SUBADDRESS 0x33, BIT 2.
06234-
056
MPEG2
DECODER
CLKIN
P[7:0]
P[15:8]
INTERLACED TO
PROGRESSIVE
YCrCb
ADV7392/
ADV7393
VSYNC
HSYNC
8
CrCb
8
Y
2
06234-
057
MPEG2
DECODER
CLKIN
P[15:8]/P[15:6]
INTERLACED TO
PROGRESSIVE
YCrCb
ADV7392/
ADV7393
VSYNC
HSYNC
8/10
2
YCrCb
06234-
058
3FF
00
XY
Cb0
Y0
Y1
Cr0
CLKIN
P[15:8]/P[15:6]
NOTES
1. 10-BIT MODE IS ENABLED USING SUBADDRESS 0x33, BIT 2.
06234-
059
MPEG2
DECODER
CLKIN
P[15:8]/P[15:6]
54MHz
ADV7392/
ADV7393
VSYNC,
HSYNC
YCrCb
8/10
YCrCb
INTERLACED TO
PROGRESSIVE
06234-
060
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