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參數(shù)資料
| 型號(hào)： | EVAL-ADV739XFEZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 22/108頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADV739XFEZ |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Advantiv® |
| 主要目的： | 視頻，視頻處理 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADV7403 |
| 主要屬性： | NTSC/PAL 數(shù)字視頻解碼器 |
| 次要屬性： | 前端板，用于 ADV7390、ADV7391、ADV7392 和 ADV7393 編碼器背端板 |
| 已供物品： | 板 |
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ADV7390/ADV7391/ADV7392/ADV7393
Data Sheet
Rev. G | Page 20 of 108
Pin No.
Mnemonic
Input/
Output
Description
ADV7390/
ADV7391
ADV7392/
ADV7393
ADV7390
WLCSP
24
30
A1
RSET
I
Controls the amplitudes of the DAC 1, DAC 2, and DAC 3
outputs. For full-drive operation (for example, into a 37.5 Ω
load), a 510 Ω resistor must be connected from RSET to
AGND. For low-drive operation (for example, into a 300 Ω
load), a 4.12 kΩ resistor must be connected from RSET to
AGND.
23
29
C2
COMP
O
Compensation Pin. Connect a 2.2 nF capacitor from COMP
to VAA.
B1
DAC 1
O
DAC Output. Full-drive and low-drive capable DAC
22, 21, 20
28, 27, 26
DAC 1, DAC 2,
DAC 3
O
DAC Outputs. Full-drive and low-drive capable DACs.
12
14
F3
SCL
I
I2C Clock Input.
11
13
F2
SDA
I/O
I2C Data Input/Output.
10
12
E3
ALSB
I
14
20
D3
RESET
I
Resets the on-chip timing generator and sets the ADV739x
into its default mode.
19
25
C1
VAA
P
Analog Power Supply (2.7 V or 3.3 V).
5, 28
6, 35
A3, D4
VDD
P
Digital Power Supply (1.8 V). For dual-supply
configurations, VDD can be connected to other 1.8 V
supplies through a ferrite bead or suitable filtering.
1
A5
VDD_IO
P
Input/Output Digital Power Supply (1.8 V or 3.3 V).
17
23
E1
PVDD
P
PLL Power Supply (1.8 V). For dual-supply configurations,
PVDD can be connected to other 1.8 V supplies through a
ferrite bead or suitable filtering.
16
22
E2
EXT_LF
I
External Loop Filter for the Internal PLL.
15
21
F1
PGND
G
PLL Ground Pin.
18
24
D1
AGND
G
Analog Ground Pin.
6, 29
7, 36
C3, D5
DGND
G
Digital Ground Pin.
32
40
D2
GND_IO
G
Input/Output Supply Ground Pin.
External Pad
EPAD
G
Connect to analog ground (AGND).
1
ED = enhanced definition = 525p and 625p.
2
LSB = least significant bit. In the ADV7390/ADV7392, setting the LSB to 0 sets the I2C address to 0xD4. Setting it to 1 sets the I2C address to 0xD6. In the
ADV7391/ADV7393, setting the LSB to 0 sets the I2C address to 0x54. Setting it to 1 sets the I2C address to 0x56.
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