參數(shù)資料
型號(hào): EVAL-ADV739XFEZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 44/108頁(yè)
文件大?。?/td> 0K
描述: BOARD EVAL FOR ADV739XFEZ
標(biāo)準(zhǔn)包裝: 1
系列: Advantiv®
主要目的: 視頻,視頻處理
嵌入式:
已用 IC / 零件: ADV7403
主要屬性: NTSC/PAL 數(shù)字視頻解碼器
次要屬性: 前端板,用于 ADV7390、ADV7391、ADV7392 和 ADV7393 編碼器背端板
已供物品:
ADV7390/ADV7391/ADV7392/ADV7393
Data Sheet
Rev. G | Page 40 of 108
Table 29. Register 0x88 to Register 0x89
SR7 to
Bit Number
Reset
SR0
Register
Bit Description
7
6
5
4
3
2
1
0
Register Setting
Value
0x88
SD Mode Register 7
Reserved
0
0x00
SD noninterlaced mode
0
Disabled.
1
Enabled.
SD double buffering
0
Disabled.
1
Enabled.
SD input format
0
8-bit YCbCr input.
0
1
16-bit YCbCr input.1
1
0
10-bit YCbCr/16-bit SD RGB
input.1
1
Reserved.
SD digital noise reduction
0
Disabled.
1
Enabled.
SD gamma correction enable
0
Disabled.
1
Enabled.
SD gamma correction curve select
0
Gamma Correction Curve A.
1
Gamma Correction Curve B.
0x89
SD Mode Register 8
SD undershoot limiter
0
Disabled.
0x00
0
1
11 IRE.
1
0
6 IRE.
1
1.5 IRE.
Reserved
0
0 must be written to this bit.
Reserved
0
Reserved.
SD chroma delay
0
Disabled.
0
1
4 clock cycles.
1
0
8 clock cycles.
1
Reserved.
Reserved
0
0 must be written to these bits.
1
Available on the ADV7392/ADV7393 (40-pin devices) only.
Table 30. Register 0x8A to Register 0x98
SR7 to
Bit Number1
Reset
SR0
Register
Bit Description
7
6
5
4
3
2
1
0
Register Setting
Value
0x8A
SD Timing Register 0
SD slave/master mode
0
Slave mode.
0x08
1
Master mode.
SD timing mode
0
Mode 0.
0
1
Mode 1.
1
0
Mode 2.
1
Mode 3.
Reserved
1
SD luma delay
0
No delay.
0
1
Two clock cycles.
1
0
Four clock cycles.
1
Six clock cycles.
SD minimum luma value
0
40 IRE.
1
7.5 IRE.
SD timing reset
x
A low-high-low transition
resets the internal SD
timing counters.
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