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參數(shù)資料
| 型號(hào)： | EVAL-ADV739XFEZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 32/108頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADV739XFEZ |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Advantiv® |
| 主要目的： | 視頻，視頻處理 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADV7403 |
| 主要屬性： | NTSC/PAL 數(shù)字視頻解碼器 |
| 次要屬性： | 前端板，用于 ADV7390、ADV7391、ADV7392 和 ADV7393 編碼器背端板 |
| 已供物品： | 板 |
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Data Sheet
ADV7390/ADV7391/ADV7392/ADV7393
Rev. G | Page 3 of 108
SD Timing ........................................................................................80
REVISION HISTORY
2/13—Rev. F to Rev. G
Change to Features Section..............................................................1
Changes to Table 14 ........................................................................18
Changes to Figure 62 ......................................................................48
Changes to Ordering Guide.........................................................107
11/12—Rev. E to Rev. F
Updated Outline Dimensions......................................................105
Changes to Ordering Guide.........................................................107
2/12—Rev. D to Rev. E
Changes to Table 1 ............................................................................5
Changes to Digital Input/Output Specifications—
1.8 V Section ......................................................................................8
Changes to Table 15 ........................................................................21
Changes to Table 20 ........................................................................31
Changes to Table 23 ........................................................................34
Changes to Table 28 ........................................................................39
Changes to 16-Bit 4:4:4 RGB Mode Section................................47
Added External Sync Polarity Section..........................................51
Deleted ED/HD Nonstandard Timing Mode Section, Figure 63,
and Table 41, Renumbered Sequentially......................................51
Changed SD Subcarrier Frequency Lock, Subcarrier Phase
Reset, and Timing Reset Section to SD Subcarrier Frequency
Lock Section.....................................................................................52
Deleted Subaddress 0x84, Bits[2:1] Section, Timing Reset (TR)
Mode Section, Subcarrier Phase Reset (SCR) Mode Section,
Figure 64, and Figure 65.................................................................52
Changes to Ordering Guide.........................................................121
11/11—Rev. C to Rev. D
Changes to Features Section ............................................................1
Updated Outline Dimensions and changes to Automotive
Products Section............................................................................107
9/11—Rev. B to Rev. C
Changes to MPU Port Description Section.................................26
Changes to Ordering Guide.........................................................107
7/10—Rev. A to Rev. B
Changes to Features Section............................................................1
Change to Applications Section ......................................................5
Changes to General Description.....................................................5
Added Table 2, Renumbered Subsequent Tables ..........................5
Added Figure 2, Renumbered Subsequent Figures ......................6
Changes to Full-Drive Output Current Parameter, Table 5 ........7
Changes to Table 14 ........................................................................18
Added Figure 20..............................................................................19
Changes to Table 15 ........................................................................19
Changes to ADV7390/ADV7391 Input Configuration
Section ..............................................................................................45
Added Additional Layout Considerations for the WLCSP
Package Section ...............................................................................71
Added Figure 97..............................................................................73
Changes to Configuration Scripts Section...................................92
Changes to Subaddress 0x00, Table 66.........................................93
Changes to Subaddress 0x00, Table 80.........................................95
Changes to Subaddress 0x00, Table 83.........................................95
Changes to Subaddress 0x00, Table 97.........................................98
Updated Outline Dimensions, Added Figure 150....................106
Changes to Ordering Guide.........................................................106
3/09—Rev. 0 to Rev. A
Changes to Features Section............................................................1
Deleted Detailed Features Section, Changes to Table 1...............4
Changes to Figure 1, Added Figure 2.............................................5
Changes to Table 2, Input Clock Specifications Section, and
Analog Output Specifications Section............................................6
Changes to Digital Input/Output Specifications—3.3 V Section
and Table 5 .........................................................................................7
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