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參數(shù)資料
| 型號(hào)： | EVAL-ADV739XFEZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 36/108頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADV739XFEZ |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Advantiv® |
| 主要目的： | 視頻，視頻處理 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | ADV7403 |
| 主要屬性： | NTSC/PAL 數(shù)字視頻解碼器 |
| 次要屬性： | 前端板，用于 ADV7390、ADV7391、ADV7392 和 ADV7393 編碼器背端板 |
| 已供物品： | 板 |
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Data Sheet
ADV7390/ADV7391/ADV7392/ADV7393
Rev. G | Page 33 of 108
Table 22. Register 0x34 to Register 0x38
SR7 to
Reset
SR0
Register
Bit Description
7
6
5
4
3
2
1
0
Register Setting
Value
0x34
ED/HD Mode
Register 5
ED/HD timing reset
0
Internal ED/HD timing counters enabled.
0x48
1
Resets the internal ED/HD timing counters.
0
HSYNC output control (see Table 55).
1
ED/HD VSYNC control2
0
VSYNC output control (see Table 56).
1
Reserved
1
0
ED Macrovision disabled.
1
ED Macrovision enabled.
Reserved
0
0 must be written to this bit.
ED/HD VSYNC input/field
input
0
0 = Field input.
1
1 = VSYNC input.
ED/HD horizontal/vertical
0
Update field/line counter.
1
Field/line counter free running.
0x35
ED/HD Mode
Register 6
Reserved
0
0x00
Reserved
0
ED/HD sync on PrPb
0
Disabled.
1
Enabled.
ED/HD color DAC swap
0
DAC 2 = Pb, DAC 3 = Pr
1
DAC 2 = Pr, DAC 3 = Pb.
ED/HD gamma correction
curve select
0
Gamma Correction Curve A.
1
Gamma Correction Curve B.
ED/HD gamma correction
enable
0
Disabled.
1
Enabled.
ED/HD adaptive filter
mode
0
Mode A.
1
Mode B.
ED/HD adaptive filter
enable
0
Disabled.
1
Enabled.
0x36
ED/HD Test Pattern Y level
x
Y level value.
0xA0
0x37
ED/HD Cr level5
ED/HD Test Pattern Cr level
x
Cr level value.
0x80
0x38
ED/HD Cb level5
ED/HD Test Pattern Cb level
x
Cb level value.
0x80
1 x = Logic 0 or Logic 1.
2 Used in conjunction with ED/HD sync output enable in Subaddress 0x02, Bit 7 = 1.
3 Applies to the ADV7390 and ADV7392 only.
4 When set to 0, the horizontal/vertical counters automatically wrap around at the end of the line/field/frame of the selected standard. When set to 1, the
horizontal/vertical counters are free running and wrap around when external sync signals indicate to do so.
5 For use with ED/HD internal test patterns only (Subaddress 0x31, Bit 2 = 1).
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