參數(shù)資料
型號(hào)： EVAL-ADV739XFEZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 20/108頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADV739XFEZ
標(biāo)準(zhǔn)包裝： 1
系列： Advantiv®
主要目的： 視頻，視頻處理
嵌入式： 否
已用 IC / 零件： ADV7403
主要屬性： NTSC/PAL 數(shù)字視頻解碼器
次要屬性： 前端板，用于 ADV7390、ADV7391、ADV7392 和 ADV7393 編碼器背端板
已供物品： 板
Data Sheet
ADV7390/ADV7391/ADV7392/ADV7393
Rev. G | Page 19 of 108
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 18. ADV7390/ADV7391 Pin Configuration
Figure 19. ADV7392/ADV7393 Pin Configuration
Figure 20. ADV7390BCBZ-A Pin Configuration
Table 15. Pin Function Descriptions
Pin No.
Mnemonic
Input/
Output
Description
ADV7390/
ADV7391
ADV7392/
ADV7393
ADV7390
WLCSP
9 to 7, 4 to 2,
31, 30
F5, E5, E4, C5,
C4, B5, B4, A4
P7 to P0
I
8-Bit Pixel Port (P7 to P0). P0 is the LSB. See Table 35 for
input modes (ADV7390/ADV7391).
18 to 15, 11 to
8, 5 to 2, 39 to
37, 34
P15 to P0
I
16-Bit Pixel Port (P15 to P0). P0 is the LSB. See Table 36 for
input modes (ADV7392/ADV7393).
13
19
F4
CLKIN
I
Pixel Clock Input for HD (74.25 MHz), ED1 (27 MHz or 54 MHz),
or SD (27 MHz).
27
33
A2
HSYNC
I/O
Horizontal Synchronization Signal. This pin can also be
configured to output an SD, ED, or HD horizontal
synchronization signal. See the External Horizontal and
26
32
B2
VSYNC
I/O
Vertical Synchronization Signal. This pin can also be
configured to output an SD, ED, or HD vertical
synchronization signal. See the External Horizontal and
25
31
B3
SFL
I/O
Subcarrier Frequency Lock (SFL) Input.
PIN 1
INDICATOR
1
VDD_IO
NOTES
1. THE EXPOSED PAD SHOULD BE CONNECTED
TO ANALOG GROUND (AGND).
2
P2
3
P3
4
P4
5
VDD
6
DGND
7
P5
8
P6
24 RSET
23 COMP
22 DAC 1
21 DAC 2
20 DAC 3
19 VAA
18 AGND
17 PVDD
9
P
7
10
A
L
S
B
11
S
D
A
12
S
C
L
13
C
L
K
IN
14
R
E
S
E
T
15
P
G
N
D
16
E
X
T
_L
F
32
G
N
D
_I
O
31
P
1
30
P
0
29
D
G
N
D
28
V
D
27
H
S
Y
N
C
26
V
S
Y
N
C
25
S
FL
TOP VIEW
(Not to Scale)
ADV7390/
ADV7391
06
23
4-
01
7
TOP VIEW
(Not to Scale)
ADV7392/
ADV7393
PIN 1
INDICATOR
1
VDD_IO
2
P4
3
P5
4
P6
5
P7
6
VDD
7
DGND
8
P8
9
P9
10
P10
23 PVDD
24 AGND
25 VAA
26 DAC 3
27 DAC 2
28 DAC 1
29 COMP
30 RSET
22 EXT_LF
21 PGND
11
P
11
12
A
L
S
B
13
S
D
A
15
P
12
17
P
14
16
P
13
18
P
15
19
C
L
K
IN
20
R
E
S
E
T
14
S
C
L
33
34
P
0
35
V
D
36
D
G
N
D
37
P
1
38
P
2
39
P
3
40
G
N
D
_I
O
32 31
S
F
L
H
S
Y
N
C
V
S
Y
N
C
06
23
4-
0
18
NOTES
1. THE EXPOSED PAD SHOULD BE CONNECTED
TO ANALOG GROUND (AGND).
06
23
4-
1
47
1
A
B
C
D
E
F
234
VDD
P0
VDD_IO
RSET
DAC1
HSYNC
VSYNC
SFL
P1
P2
VAA
COMP
DGND
P3
P4
AGND
GND_IO
RESET
VDD
DGND
PVDD
EXT_LF
ALSB
P5
P6
PGND
SDA
SCL
CLKIN
P7
5
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
BALL A1 CORNER
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