ADuC832
Data Sheet
Rev. B | Page 8 of 92
VDD = 5 V
VDD = 3 V
Unit
Test Conditions/Comments
(Schmitt-Triggered Inputs)
VT+
1.3
0.95
V min
3.0
2.5
V max
VT
0.8
0.4
V min
1.4
1.1
V max
VT+ VT
0.3
V min
0.85
V max
CRYSTAL OSCILLATOR
Logic Inputs, XTAL1 Only
VINL, Input Low Voltage
0.8
0.4
V typ
VINH, Input High Voltage
3.5
2.5
V typ
XTAL1 Input Capacitance
18
pF typ
XTAL2 Output Capacitance
18
pF typ
MCU CLOCK RATE
16.78
MHz max
Programmable via PLLCON[2:0]
DIGITAL OUTPUTS
Output High Voltage (VOH)
2.4
V min
VDD = 4.5 V to 5.5 V
4.0
V typ
ISOURCE = 80 μA
2.4
V min
VDD = 2.7 V to 3.3 V
2.6
V typ
ISOURCE = 20 μA
Output Low Voltage (VOL)
ALE, Port 0 and Port 2
0.4
V max
ISINK = 1.6 mA
0.2
V typ
ISINK = 1.6 mA
Port 3
0.4
V max
ISINK = 4 mA
SCLOCK/SDATA
0.4
V max
ISINK = 8 mA, I2C enabled
Floating State Leakage Curre
nt4±10
μA max
±1
μA typ
Floating State Output Capacitance
10
pF typ
START-UP TIME
At any Core_CLK
At Power-On
500
ms typ
From Idle Mode
100
μs typ
From Power-Down Mode
Wakeup with INT0 Interrupt
150
400
μs typ
Wakeup with SPI/I2C Interrupt
150
400
μs typ
Wakeup with External Reset
150
400
μs typ
After External Reset in Normal Mode
30
ms typ
After WDT Reset in Normal Mode
3
ms typ
Controlled via WDCON SFR
Power Supply Voltages
AVDD/DVDD AGND
2.7
V min
AVDD/DVDD = 3 V nom
3.3
V max
4.5
V min
AVDD/DVDD = 5 V nom
5.5
V max
Power Supply Currents Normal Mode
6
3
mA max
Core_CLK = 2.097 MHz
AVDD Current
1.7
mA max
Core_CLK = 2.097 MHz
DVDD Current
23
12
mA max
Core_CLK = 16.78 MHz
20
10
mA typ
Core_CLK = 16.78 MHz
AVDD Current
1.7
mA max
Core_CLK = 16.78 MHz
Power Supply Currents Idle Mode
DVDD Current
4
2
mA typ
Core_CLK = 2.097 MHz
AVDD Current
0.14
mA typ
Core_CLK = 2.097 MHz
10
5
mA max
Core_CLK = 16.78 MHz
9
4
mA typ
Core_CLK = 16.78 MHz
AVDD Current
0.14
mA typ
Core_CLK = 16.78 MHz