參數(shù)資料
型號： EVAL-ADUC832QSZ
廠商： Analog Devices Inc
文件頁數(shù)： 40/92頁
文件大小： 0K
描述： KIT DEV FOR ADUC832 QUICK START
產(chǎn)品培訓(xùn)模塊： Process Control
標(biāo)準(zhǔn)包裝： 1
系列： QuickStart™ 套件
類型： MCU
適用于相關(guān)產(chǎn)品： ADuC832
所含物品： 評估板，線纜，電源，軟件和文檔
其它名稱： EVAL-ADUC832QS
EVAL-ADUC832QS-ND
Data Sheet
ADuC832
Rev. B | Page 45 of 92
NONVOLATILE FLASH/EE MEMORY
FLASH/EE MEMORY OVERVIEW
The ADuC832 incorporates Flash/EE memory technology on
chip to provide the user with nonvolatile, in-circuit, reprogramma-
ble code and data memory space. Flash/EE memory is a relatively
recent type of nonvolatile memory technology and is based on a
single transistor cell architecture.
This technology is basically an outgrowth of EPROM technol-
ogy and was developed through the late 1980s. Flash/EE memory
takes the flexible in-circuit reprogrammable features of EEPROM
and combines them with the space efficient/density features of
EPROM (see Figure 47).
Because Flash/EE technology is based on a single transistor cell
architecture, a Flash memory array, like EPROM, can be imple-
mented to achieve the space efficiencies or memory densities
required by a given design. Like EEPROM, Flash memory can
be programmed in-system at a byte level, although it must first
be erased, the erase being performed in page blocks. Thus, Flash
memory is often and more correctly referred to as Flash/EE
memory.
FLASH/EE MEMORY
TECHNOLOGY
SPACE EFFICIENT/
DENSITY
IN-CIRCUIT
REPROGRAMMABLE
EPROM
TECHNOLOGY
EEPROM
TECHNOLOGY
02987-
036
Figure 47. Flash/EE Memory Development
Overall, Flash/EE memory represents a step closer to the
ideal memory device that includes nonvolatility, in-circuit
programmability, high density, and low cost. Incorporated in
the ADuC832, Flash/EE memory technology allows the user
to update program code space in-circuit, without the need to
replace one-time programmable (OTP) devices at remote
operating nodes.
FLASH/EE MEMORY AND THE ADUC832
The ADuC832 provides two arrays of Flash/EE memory for
user applications. There are 62 kB of Flash/EE program space
provided on chip to facilitate code execution without any
external discrete ROM device requirements. The program
memory can be programmed in-circuit using the serial down-
load mode provided, using conventional third party memory
programmers, or via a user defined protocol that can configure
it as data if required.
A 4 kB Flash/EE data memory space is also provided on chip.
This can be used as a general-purpose nonvolatile scratchpad
area. User access to this area is via a group of six SFRs. This
space can be programmed at the byte level, although it must
first be erased in 4-byte pages.
ADUC832 FLASH/EE MEMORY RELIABILITY
The Flash/EE program and data memory arrays on the
ADuC832 are fully qualified for two key Flash/EE memory
characteristics, namely Flash/EE memory cycling endurance
and Flash/EE memory data retention.
Endurance quantifies the ability of the Flash/EE memory to be
cycled through many program, read, and erase cycles. In real
terms, a single Flash/EE memory endurance cycle is composed
of the following four independent, sequential events:
Initial page erase sequence
Read/verify sequence
Byte program sequence
Second read/verify sequence
In reliability qualification, every byte in both the program and
data Flash/EE memory is cycled from 00H to FFH until a first
fail is recorded, signifying the endurance limit of the on-chip
Flash/EE memory.
As indicated in the Specifications section, the ADuC832 Flash/
EE memory endurance qualification has been carried out in
accordance with JEDEC Specification A117 over the industrial
temperature range of 40°C to +25°C and +85°C to +125°C. The
results allow the specification of a minimum endurance value
over supply and temperature of 100,000 cycles, with an endur-
ance value of 700,000 cycles being typical of operation at 25°C.
Retention quantifies the ability of the Flash/EE memory to
retain its programmed data over time. Again, the ADuC832 has
been qualified in accordance with the formal JEDEC retention
lifetime specification (A117) at a specific junction temperature
(TJ = 55°C). As part of this qualification procedure, the Flash/
EE memory is cycled to its specified endurance limit described
previously, before data retention is characterized. This means
that the Flash/EE memory is guaranteed to retain its data for its
full specified retention lifetime every time the Flash/EE memory is
reprogrammed. It should also be noted that retention lifetime,
based on an activation energy of 0.6 eV, derates with TJ, as shown
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