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| 型號(hào)： | EVAL-ADUC832QSZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 62/92頁(yè) |
| 文件大小： | 0K |
| 描述： | KIT DEV FOR ADUC832 QUICK START |
| 產(chǎn)品培訓(xùn)模塊： | Process Control |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuickStart™ 套件 |
| 類(lèi)型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADuC832 |
| 所含物品： | 評(píng)估板，線(xiàn)纜，電源，軟件和文檔 |
| 其它名稱(chēng)： | EVAL-ADUC832QS EVAL-ADUC832QS-ND |
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Data Sheet
ADuC832
Rev. B | Page 65 of 92
TIME INTERVAL COUNTER (TIC)
A time interval counter is provided on chip for counting longer
intervals than the standard 8051-compatible timers are capable of.
The TIC is capable of timeout intervals ranging from 1/128 second
to 255 hours. Furthermore, this counter is clocked by the exter-
nal 32.768 kHz crystal rather than the core clock, and has the
ability to remain active in power-down mode and time long
power-down intervals. This has obvious applications for remote
battery-powered sensors where regular widely spaced readings
are required. Note that instructions to the TIC SFRs are also
clocked at 32.768 kHz, and sufficient time must be allowed in
user code for these instructions to execute.
Six SFRs are associated with the time interval counter, TIMECON
being its control register. Depending on the configuration of the
ITS0 and ITS1 bits in TIMECON, the selected time counter regis-
ter overflow clocks the interval counter. When this counter is
equal to the time interval value loaded in the INTVAL SFR, the
TII bit (TIMECON[2]) is set and generates an interrupt if
enabled. If the ADuC832 is in power-down mode, again with
the TIC interrupt enabled, the TII bit wakes up the device and
resumes code execution by vectoring directly to the TIC interrupt
service vector address at 0053H. The TIC-related SFRs are
described in the following sections. Note also that the timebase
SFRs can be written initially with the current time; the TIC can
then be controlled and accessed by user software. In effect, this
facilitates the implementation of a real-time clock. A block
diagram of the TIC is shown in Figure 65.
8-BIT
PRESCALER
HUNDREDTHS COUNTER
HTHSEC
SECOND COUNTER
SEC
MINUTE COUNTER
MIN
HOUR COUNTER
HOUR
TIEN
INTERVAL TIMEOUT
TIME INTERVAL COUNTER INTERRUPT
8-BIT
INTERVAL COUNTER
TIMER INTVAL
INTVAL
INTERVAL
TIMEBASE
SELECTION
MUX
TCEN
32.768kHz EXTERNAL CRYSTAL
ITS0, ITS1
COMPARE
COUNT = INTVAL
02987-
054
Figure 65. TIC, Simplified Block Diagram
TIMECON (TIC CONTROL REGISTER)
SFR Address:
A1H
Power-On Default Value:
00H
Bit Addressable:
No
Table 33. TIMECON SFR Bit Designations
Bit
Name
Description
[7]
Reserved
Reserved for future use.
[6]
TFH
Twenty-four hour select bit. Set by the user to enable the hour counter to count from 0 to 23. Cleared by the user to
enable the hour counter to count from 0 to 255.
[5:4]
ITS[1:0]
Interval timebase selection bits. Written by user to determine the interval counter update rate.
ITS1
ITS0
Interval Timebase
0
1/128 second
0
1
Seconds
1
0
Minutes
1
Hours
[3]
STI
Single-time interval bit. Set by the user to generate a single interval timeout. If set, a timeout clears the TIEN bit. Cleared
by the user to allow the interval counter to be automatically reloaded and starts counting again at each interval timeout.
[2]
TII
TIC interrupt bit. Set when the 8-bit interval counter matches the value in the INTVAL SFR. Cleared by user software.
[1]
TIEN
Time interval enable bit. Set by the user to enable the 8-bit time interval counter. Cleared by the user to disable the
interval counter.
[0]
TCEN
Time clock enable bit. Set by the user to enable the time clock to the time interval counters. Cleared by the user to
disable the clock to the time interval counters and to reset the time interval SFRs to the last value written to them by the
user. The time registers (HTHSEC, SEC, MIN, and hour) can be written while TCEN is low.
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