參數(shù)資料
型號(hào)： EVAL-ADUC832QSZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 50/92頁(yè)
文件大?。?/td> 0K
描述： KIT DEV FOR ADUC832 QUICK START
產(chǎn)品培訓(xùn)模塊： Process Control
標(biāo)準(zhǔn)包裝： 1
系列： QuickStart™ 套件
類(lèi)型： MCU
適用于相關(guān)產(chǎn)品： ADuC832
所含物品： 評(píng)估板，線纜，電源，軟件和文檔
其它名稱： EVAL-ADUC832QS
EVAL-ADUC832QS-ND
ADuC832
Data Sheet
Rev. B | Page 54 of 92
ON-CHIP PLL
The ADuC832 is intended for use with a 32.768 kHz watch
crystal. A PLL locks onto a multiple (512) of this to provide a
stable 16.78 MHz clock for the system. The core can operate at
this frequency or at binary submultiples of it to allow power
saving in cases where maximum core performance is not
required. The default core clock is the PLL clock divided by 8 or
2.097152 MHz. The ADC clocks are also derived from the PLL
clock, with the modulator rate being the same as the crystal
oscillator frequency. The choice of frequencies ensures that the
modulators and the core are synchronous, regardless of the core
clock rate. The PLL control register is PLLCON.
PLLCON (PLL CONTROL REGISTER)
SFR Address:
D7H
Power-On Default Value:
53H
Bit Addressable:
No
Table 26. PLLCON SFR Bit Designations
Bit
Name
Description
[7]
OSC_PD
Oscillator power-down bit.
Set by user to halt the 32 kHz oscillator in power-down mode.
Cleared by user to enable the 32 kHz oscillator in power-down mode. This feature allows the TIC to continue counting
even in power-down mode.
[6]
LOCK
PLL lock bit. This is a read-only bit.
Set automatically at power-on to indicate the PLL loop is correctly tracking the crystal clock. If the external crystal
becomes subsequently disconnected, the PLL rails and the core halt.
Cleared automatically at power-on to indicate the PLL is not correctly tracking the crystal clock. This may be due to the
absence of a crystal clock or an external crystal at power-on. In this mode, the PLL output can be 16.78 MHz ± 20%.
[5]
Reserved
Reserved for future use; should be written with 0.
[4]
Reserved
Reserved for future use; should be written with 0.
[3]
FINT
Fast interrupt response bit.
Set by user, enabling the response to any interrupt to be executed at the fastest core clock frequency, regardless of the
configuration of the CD[2:0] bits. Once user code has returned from an interrupt, the core resumes code execution at the
core clock selected by the CD[2:0] bits.
Cleared by user to disable the fast interrupt response feature.
[2:0]
CD[2:0]
CPU (core clock) divider bits. These bits determine the frequency at which the microcontroller core operates.
CD2
CD1
CD0
Core Clock Frequency, fCORE (MHz)
0
16.78
0
1
8.388608
0
1
0
4.194304
0
1
2.097152 (default core clock frequency)
1
0
1.048576
1
0
1
0.524288
1
0
0.262144
1
0.131072
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