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參數(shù)資料
| 型號(hào)： | EVAL-ADUC832QSZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 55/92頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | KIT DEV FOR ADUC832 QUICK START |
| 產(chǎn)品培訓(xùn)模塊： | Process Control |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuickStart™ 套件 |
| 類(lèi)型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADuC832 |
| 所含物品： | 評(píng)估板，線纜，電源，軟件和文檔 |
| 其它名稱(chēng)： | EVAL-ADUC832QS EVAL-ADUC832QS-ND |
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Data Sheet
ADuC832
Rev. B | Page 59 of 92
SPIDAT (SPI Data Register)
SFR Address:
F7H
Power-On Default Value:
00H
Bit Addressable:
No
The SPIDAT SFR is written by the user to transmit data over the
SPI interface, or read by the user read data just received by the
SPI interface.
USING THE SPI INTERFACE
Depending on the configuration of the bits in the SPICON SFR
shown in Table 28, the ADuC832 SPI interface transmits or
receives data in a number of possible modes. Figure 63 shows all
possible ADuC832 SPI configurations and the timing relationships
and synchronization between the signals involved. Also shown
is the SPI interrupt bit (ISPI) and how it is triggered at the end of
each byte-wide communication.
SCLOCK
(CPOL = 1)
SCLOCK
(CPOL = 0)
(CPHA = 1)
(CPHA = 0)
SAMPLE INPUT
ISPI FLAG
DATA OUTPUT
ISPI FLAG
SAMPLE INPUT
DATA OUTPUT
×
MSB BIT 6 BIT 5
×
BIT4 BIT 3 BIT2 BIT1 LSB
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
SS
02
987-
0
52
Figure 63. SPI Timing, All Modes
SPI INTERFACE—MASTER MODE
In master mode, the SCLOCK pin is always an output and
generates a burst of eight clocks whenever user code writes to
the SPIDAT register. The SCLOCK bit rate is determined by
SPR0 and SPR1 in SPICON. It should also be noted that the SS
pin is not used in master mode. If the ADuC832 needs to assert
the SS pin on an external slave device, a port digital output pin
should be used.
In master mode, a byte transmission or reception is initiated by
a write to SPIDAT. Eight clock periods are generated via the
SCLOCK pin and the SPIDAT byte being transmitted via MOSI.
With each SCLOCK period, a data bit is also sampled via MISO.
After eight clocks, the transmitted byte is completely transmitted
and the input byte waits in the input shift register. The ISPI flag
is set automatically and an interrupt occurs if enabled. The
value in the shift register is latched into SPIDAT.
SPI INTERFACE—SLAVE MODE
In slave mode, the SCLOCK is an input. The SS pin must also
be driven low externally during the byte communication.
Transmission is also initiated by a write to SPIDAT. In slave mode,
a data bit is transmitted via MISO and a data bit is received via
MOSI through each input SCLOCK period. After eight clocks,
the transmitted byte is completely transmitted and the input
byte waits in the input shift register. The ISPI flag is set automati-
cally and an interrupt occurs if enabled. The value in the shift
register is latched into SPIDAT only when the transmission/
reception of a byte has been completed. The end of transmission
occurs after the eighth clock has been received if CPHA = 1, or
when SS returns high if CPHA = 0.
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