參數(shù)資料
型號: EVAL-ADUC832QSZ
廠商: Analog Devices Inc
文件頁數(shù): 3/92頁
文件大?。?/td> 0K
描述: KIT DEV FOR ADUC832 QUICK START
產(chǎn)品培訓模塊: Process Control
標準包裝: 1
系列: QuickStart™ 套件
類型: MCU
適用于相關(guān)產(chǎn)品: ADuC832
所含物品: 評估板,線纜,電源,軟件和文檔
其它名稱: EVAL-ADUC832QS
EVAL-ADUC832QS-ND
Data Sheet
ADuC832
Rev. B | Page 11 of 92
Table 3. External Program Memory Read Cycle
Parameter1
Description
16.78 MHz Core_CLK
Variable Clock
Min
Max
Min
Max
Unit
tLHLL
ALE pulse width
79
2tCK 40
ns
tAVLL
Address valid to ALE low
19
tCK 40
ns
tLLAX
Address hold after ALE low
29
tCK 30
ns
tLLIV
ALE low to valid instruction in
138
4tCK 100
ns
tLLPL
ALE low to PSEN low
29
tCK 30
ns
tPLPH
PSEN pulse width
133
3tCK 45
ns
tPLIV
PSEN low to valid instruction in
73
3tCK 105
ns
tPXIX
Instruction in, hold after PSEN
0
ns
tPXIZ
Instruction in, float after PSEN
34
tCK 25
ns
tAVIV
Address to valid instruction in
193
5tCK 105
ns
tPLAZ
PSEN low to address float
25
ns
tPHAX
Address hold after PSEN high
0
ns
MCLK
ALE (O)
PSEN (O)
PORT 0 (I/O)
PORT 2 (O)
tLHLL
tAVLL
tLLPL
tPLPH
tLLIV
tPLIV
tPLAZ
tLLAX
tPXIX
tPXIZ
tPHAX
tAVIV
PCL (OUT)
INSTRUCTION
(IN)
PCH
02
98
7-
0
88
Figure 5. External Program Memory Read Cycle
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