Data Sheet
ADuC832
Rev. B | Page 7 of 92
VDD = 5 V
VDD = 3 V
Unit
Test Conditions/Comments
DISABLED
Resolution
12
Bits
Relative Accuracy
±3
LSB typ
Differential Nonlinearit
y111
LSB max
Guaranteed 12-bit monotonic
±1/2
LSB typ
Offset Error
±5
mV max
VREF range
Gain Error
0.3
% typ
VREF range
0.5
% max
% of full scale on DAC1
Analog outputs
Voltage Range 0
0 to VREF
V typ
DAC VREF = 2.5 V
REFERENCE INPUT/OUTPUT
Output Voltage (VREF)
2.5
V typ
Accuracy
±2.5
% max
Of VREF measured at the CREF pin
Power Supply Rejection
47
dB typ
Reference Temperature Coefficient
±100
ppm/°C
typ
Internal VREF Power-On Time
80
ms typ
External Reference Inpu
t15VREF and CREF pins shorted
0.1
V min
VDD
V max
Input Impedance
20
kΩ typ
Input Leakage
1
μA max
Internal band gap deselected via
ADCCON1[6]
POWER SUPPLY MONITOR (PSM)
DVDD Trip Point Selection Range
2.63
V min
Four trip points selectable in this range
4.37
V max
programmed via TPD1 and TPD0 in PSMCON
DVDD Power Supply Trip Point Accuracy
±3.5
% max
Timeout Period
0
ms min
Nine timeout periods
2000
ms max
Selectable in this range
FLASH/EE MEMORY RELIABILITY CHARACTERISTIC
S16100,000
Cycles min
100
Years min
DIGITAL INPUTS
Input High Voltage (V
INH)42.4
2
V min
Input Low Voltage (V
INL)40.8
0.4
V max
Input Leakage Current (Port 0, EA)
±10
μA max
VIN = 0 V or VDD
±1
μA typ
VIN = 0 V or VDD
Logic 1 Input Current (All Digital Inputs)
±10
μA max
VIN = VDD
±1
μA typ
VIN = VDD
Logic 0 Input Current (Port 1, Port 2, and Port 3)
75
25
μA max
40
15
μA typ
VIL = 450 mV
Logic 1-to-Logic 0 Transition Current (Port 2, Port 3)
660
250
μA max
VIL = 2 V
400
140
μA typ
VIL = 2 V