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| 型號： | EVAL-ADUC832QSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 46/92頁 |
| 文件大小： | 0K |
| 描述： | KIT DEV FOR ADUC832 QUICK START |
| 產(chǎn)品培訓(xùn)模塊： | Process Control |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuickStart™ 套件 |
| 類型： | MCU |
| 適用于相關(guān)產(chǎn)品： | ADuC832 |
| 所含物品： | 評估板，線纜，電源，軟件和文檔 |
| 其它名稱： | EVAL-ADUC832QS EVAL-ADUC832QS-ND |
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ADuC832
Data Sheet
Rev. B | Page 50 of 92
ADUC832 CONFIGURATION SFR (CFG832)
The CFG832 SFR contains the necessary bits to configure the
internal XRAM, external clock select, PWM output selection,
DAC buffer, and the extended SP. By default, it configures the
user into 8051 mode; that is, extended SP is disabled and the
internal XRAM is disabled.
CFG832 (ADuC832 Configuration SFR)
SFR Address:
AFH
Power-On Default Value:
00H
Bit Addressable:
No
Table 24. CFG832 SFR Bit Designations
Bit
Name
Description
[7]
EXSP
Extended SP enable.
When set to 1 by the user, the stack rolls over from SPH/SP = 00FFH to SPH/SP = 0100H.
When set to 0 by the user, the stack rolls over from SP = FFH to SP = 00H.
[6]
PWPO
PWM pinout selection.
When set to 1 by the user, the PWM output pins are selected as P3.4 and P3.3.
When set to 0 by the user, the PWM output pins are selected as P2.6 and P2.7.
[5]
DBUF
DAC output buffer.
When set to 1 by the user, the DAC output buffer is bypassed.
When set to 0 by the user, the DAC output buffer is enabled.
[4]
EXTCLK
Set by the user to 1 to select an external clock input on P3.4.
Set by the user to 0 to use the internal PLL clock.
[3]
RSVD
Reserved. This bit should always contain 0.
[2]
RSVD
Reserved. This bit should always contain 0.
[1]
RSVD
Reserved. This bit should always contain 0.
[0]
XRAMEN
XRAM enable bit.
When set to 1 by the user, the internal XRAM is mapped into the lower 2 kB of the external address space.
When set to 0 by the user, the internal XRAM is not accessible and the external data memory is mapped into the lower
2 kB of external data memory.
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