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| 型號： | EVAL-ADUC7036QSPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數： | 99/132頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADUC7036 |
| 設計資源： | EVAL-ADUC7036 Schematic & Brd Outline EVAL ADUC7036 Gerber Files |
| 標準包裝： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 主要目的： | 電源管理，電池監(jiān)控器 |
| 嵌入式： | 是，MCU，16/32 位 |
| 已用 IC / 零件： | ADuC7036 |
| 已供物品： | 板，線纜，文檔，仿真器，電源，軟件 |
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ADuC7036
Rev. C | Page 69 of 132
Normal Interrupt (IRQ) Request
The IRQ request is the exception signal allowed to enter the
processor in IRQ mode. It is used to service general-purpose
interrupt handling of internal and external events.
All 32 bits of the IRQSTA MMR are OR’ed to create a single
IRQ signal to the ARM7TDMI core. The four 32-bit registers
dedicated to IRQ are described in the IRQSTA Register to the
IRQCLR Register sections.
IRQSTA Register
Name: IRQSTA
Adress: 0xFFFF0000
Default Value: 0x00000000
Access: Read only
Function: This register provides the status of the IRQ source
that is currently enabled by IRQ source status (see Figure 32).
When a bit in this register is set to 1, the corresponding source
generates an active IRQ request to the ARM7TDMI core. There
is no priority encoder or interrupt vector generation. This
function is implemented in software in a common interrupt
handler routine.
IRQSIG Register
Name: IRQSIG
Address: 0xFFFF0004
Default Value: 0x00000000
Access: Read only
Function: This 32-bit register reflects the status of the different
IRQ sources. If a peripheral generates an IRQ signal, the corres-
ponding bit in the IRQSIG is set; otherwise, the corresponding
bit is cleared. The IRQSIG bits are cleared when the interrupt in
the particular peripheral is cleared. All IRQ sources can be masked
in the IRQEN MMR. IRQSIG is read only.
IRQEN Register
Name: IRQEN
Address: 0xFFFF0008
Default Value: 0x00000000
Access: Read/write
Function: This register provides the value of the current enable
mask. When a bit in this register is set to 1, the corresponding
source request is enabled to create an IRQ exception signal.
When a bit is set to 0, the corresponding source request is
disabled or masked and does not create an IRQ exception signal.
The IRQEN register cannot be used to disable an interrupt.
IRQCLR Register
Name: IRQCLR
Address: 0xFFFF000C
Access: Write only
Function: This register allows the IRQEN register to clear to
mask an interrupt source. Each bit set to 1 clears the corresponding
bit in the IRQEN register without affecting the remaining bits.
When used as a pair of registers, IRQEN and IRQCLR allow
independent manipulation of the enable mask without requiring
an automatic read-modify-write instruction.
Fast Interrupt Request (FIQ)
The FIQ is the exception signal allowed to enter the processor in
FIQ mode. It is provided to service data transfer or communication
channel tasks with low latency. The FIQ interface is identical
to the IRQ interface and provides the second-level interrupt
(highest priority). Four 32-bit registers are dedicated to FIQ:
FIQSIG, FIQEN, FIQCLR, and FIQSTA.
All 32 bits of the FIQSTA MMR are OR’ed to create the FIQ signal
to the core and to Bit 0 of both the FIQ and IRQ registers (FIQ
source).
The logic for FIQEN and FIQCLR does not allow an interrupt
source to be enabled in both IRQ and FIQ masks. As a side effect,
a bit set to 1 in FIQEN clears the same bit in IRQEN. Likewise, a
bit set to 1 in IRQEN clears the same bit in FIQEN. An interrupt
source can be disabled in both IRQEN and FIQEN masks.
Programmed Interrupts
Because the programmed interrupts are not maskable, they are
controlled by another register, SWICFG, that writes into both
IRQSTA and IRQSIG registers and/or the FIQSTA and FIQSIG
registers at the same time.
The 32-bit register dedicated to software interrupt is SWICFG;
it is described in Table 51. This MMR allows the control of a pro-
grammed source interrupt.
Table 51. SWICFG MMR Bit Designations
Bit
Description
31 to 3
Reserved.
2
Programmed interrupt FIQ.
Setting/clearing this bit corresponds to setting/clearing
Bit 1 of FIQSTA and FIQSIG.
1
Programmed interrupt IRQ.
Setting/clearing this bit corresponds to setting/clearing
Bit 1 of IRQSTA and IRQSIG.
0
Reserved.
Note that any interrupt signal must be active for at least the
minimum interrupt latency time to be detected by the interrupt
controller and by the user in the IRQSTA or FIQSTA register.
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