參數(shù)資料
型號： EVAL-ADUC7036QSPZ
廠商： Analog Devices Inc
文件頁數(shù)： 116/132頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADUC7036
設(shè)計資源： EVAL-ADUC7036 Schematic & Brd Outline
EVAL ADUC7036 Gerber Files
標(biāo)準(zhǔn)包裝： 1
系列： QuickStart™ PLUS 套件
主要目的： 電源管理，電池監(jiān)控器
嵌入式： 是，MCU，16/32 位
已用 IC / 零件： ADuC7036
已供物品： 板，線纜，文檔，仿真器，電源，軟件
ADuC7036
Rev. C | Page 84 of 132
GENERAL-PURPOSE I/O
The ADuC7036 features nine general-purpose bidirectional input/
output (GPIO) pins. In general, many of the GPIO pins have
multiple functions that can be configured by user code. By default,
the GPIO pins are configured in GPIO mode. All GPIO pins have
an internal pull-up resistor with a sink capability of 0.8 mA and
a source capability of 0.1 mA.
The nine GPIOs are grouped into three ports: Port0, Port1, and
Port2. Port0 is five bits wide. Port1 and Port2 are each two bits
wide. The GPIO assignment within each port is detailed in
Table 58. A typical GPIO structure is shown Figure 40.
1ONLY AVAILABLE ON GPIO_0, GPIO_5, GPIO_7, AND GPIO_8.
GPIO
REG_DVDD
OUTPUT DRIVE ENABLE
GPxDAT[31:24]
OUTPUT DATA
GPxDAT[23:16]
INPUT DATA
GPxDAT[7:0]
GPIO IRQ1
07
47
4-
03
7
Figure 40. Typical GPIO Structure
External interrupts are present on GPIO_0, GPIO_5, GPIO_7,
and GPIO_8. These interrupts are level triggered and active high.
These interrupts are not latched; therefore, the interrupt source
must be present until either IRQSTA or FIQSTA are interrogated.
The interrupt source must be active for at least one CD-divided
core clock to guarantee recognition.
All port pins are configured and controlled by three sets (one
set for each port) of four port-specific MMRs, as follows:
GPxCON: Portx control register
GPxDAT: Portx configuration and data register
GPxSET: Portx data set
GPxCLR: Portx data clear
where x corresponds to the port number (0, 1, or 2).
During normal operation, user code can control the function
and state of the external GPIO pins using these general-purpose
registers. All GPIO pins retain their external level (high or low)
during power-down (POWCON) mode.
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