參數(shù)資料
型號： EVAL-ADUC7036QSPZ
廠商： Analog Devices Inc
文件頁數(shù)： 15/132頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR ADUC7036
設計資源： EVAL-ADUC7036 Schematic & Brd Outline
EVAL ADUC7036 Gerber Files
標準包裝： 1
系列： QuickStart™ PLUS 套件
主要目的： 電源管理，電池監(jiān)控器
嵌入式： 是，MCU，16/32 位
已用 IC / 零件： ADuC7036
已供物品： 板，線纜，文檔，仿真器，電源，軟件
ADuC7036
Rev. C | Page 111 of 132
SPI Control Register
Name: SPICON
Address: 0xFFFF0A10
Default Value: 0x0000
Access: Read/write
Function: This 16-bit MMR configures the serial peripheral interface.
Table 89. SPICON MMR Bit Designations
Bit
Description
15 to 13
Reserved.
12
Continuous transfer enable.
Set by the user to enable continuous transfer. In master mode, the transfer continues until no valid data is available in
the SPITX register. SS is asserted and remains asserted for the duration of each 8-bit serial transfer until SPITX is empty.
Cleared by the user to disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data
exists in the SPITX register, a new transfer is initiated after a stall period.
11
Loopback enable.
Set by the user to connect MISO to MOSI and test software.
Cleared by the user to be in normal mode.
10
Slave output enable.
Set by the user to enable the slave output.
Cleared by the user to disable the slave output.
9
Slave select input enable.
Set by the user in master mode to enable the output.
Cleared by the user to disable the output.
8
SPIRX overflow overwrite enable.
Set by the user; the valid data in the SPIRX register is overwritten by the new serial byte received.
Cleared by the user; the new serial byte received is discarded.
7
SPITX underflow mode.
Set by the user to transmit the previous data.
Cleared by the user to transmit 0.
6
Transfer and interrupt mode (master mode).
Set by the user to initiate a transfer with a write to the SPITX register. An interrupt occurs when SPITX is empty.
Cleared by the user to initiate a transfer with a read of the SPIRX register. An interrupt occurs when SPIRX is full.
5
LSB first transfer enable bit.
Set by the user; the LSB is transmitted first.
Cleared by the user; the MSB is transmitted first.
4
Reserved.
3
Serial clock polarity mode bit.
Set by the user; the serial clock idles high.
Cleared by the user; the serial clock idles low.
2
Serial clock phase mode bit.
Set by the user; the serial clock pulses at the beginning of each serial bit transfer.
Cleared by the user; the serial clock pulses at the end of each serial bit transfer.
1
Master mode enable bit.
Set by the user to enable master mode.
Cleared by the user to enable slave mode.
0
SPI enable bit.
Set by the user to enable the SPI.
Cleared by the user to disable the SPI.
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