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| 型號(hào)： | EVAL-ADUC7036QSPZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 88/132頁(yè) |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR ADUC7036 |
| 設(shè)計(jì)資源： | EVAL-ADUC7036 Schematic & Brd Outline EVAL ADUC7036 Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 主要目的： | 電源管理，電池監(jiān)控器 |
| 嵌入式： | 是，MCU，16/32 位 |
| 已用 IC / 零件： | ADuC7036 |
| 已供物品： | 板，線纜，文檔，仿真器，電源，軟件 |
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ADuC7036
Rev. C | Page 59 of 132
ADC CALIBRATION
As shown in detail in the top-level diagrams (Figure 18 and
Figure 19), the signal flow through all ADC channels can be
described as follows:
1.
An input voltage is applied through an input buffer (and
through PGA in the case of the I-ADC) to the Σ-Δ modulator.
2.
The modulator output is applied to a programmable digital
decimation filter.
3.
The filter output result is then averaged if chopping is used.
4.
An offset value (ADCxOF) is subtracted from the result.
5.
This result is scaled by a gain value (ADCxGN).
6.
The result is formatted as twos complement/offset binary
and rounded to 16 bits or clamped to ±full scale.
Each ADC has a specific offset and gain correction or calibra-
tion coefficient associated with it that are stored in MMR-based
offset and gain registers (ADCxOF and ADCxGN). The offset
and gain registers can be used to remove offsets and gain errors
within the part, as well as system-level offset and gain errors
external to the part.
These registers are configured at power-on with a factory-
programmed calibration value. These factory-set calibration
values vary from part to part, reflecting the manufacturing
variability of internal ADC circuits. However, these registers
can also be overwritten by user code if the ADC is in idle mode
and are automatically overwritten if an offset or gain calibration
cycle is initiated by the user through the ADC operation mode
configuration bits in the ADCMDE[2:0] MMR. Two types of
automatic calibration are available to the user: self-calibration
or system calibration.
Self-Calibration
In self-calibration of offset errors, the ADC generates its
calibration coefficient based on an internally generated 0 V,
whereas in self-calibration of gain errors, the coefficient is
based on the full-scale voltage. Although self-calibration
can correct offset and gain errors within the ADC, it cannot
compensate for external errors in the system, such as shunt
resistor tolerance/drift and external offset voltages.
Note that in self-calibration mode, ADC0GN must contain the
values for PGA = 1 before a calibration scheme is started.
System Calibration
In system calibration of offset errors, the ADC generates its
calibration coefficient based on an externally generated zero-
scale voltage, whereas in system calibration of gain errors, the
coefficient is based on the full-scale voltage. The calibration
coefficient is applied to the external ADC input for the duration
of the calibration cycle.
The duration of an offset calibration is a single conversion cycle
(3/fADC chop off, 2/fADC chop on) before returning the ADC to
idle mode. A gain calibration is a two-stage process and, there-
fore, takes twice as long as an offset calibration cycle. When a
calibration cycle is initiated, any ongoing ADC conversion is
immediately halted, the calibration is automatically performed
at the ADC update rate programmed in ADCFLT, and the ADC
is always returned to idle after any calibration cycle. It is strongly
recommended that ADC calibration be initiated at as low an
ADC update rate as possible (and, therefore, requires a high SF
value in ADCFLT) to minimize the impact of ADC noise during
calibration.
Using the Offset and Gain Calibration
If the chop enable bit, ADCFLT[15], is enabled, internal ADC
offset errors are minimized and an offset calibration may not be
required. If chopping is disabled, however, an initial offset
calibration is required and may need to be repeated, particularly
after a large change in temperature.
Depending on system accuracy requirements, a gain calibration,
particularly in the context of the I-ADC (with internal PGA), may
need to be performed at all relevant system gain ranges. If it is
not possible to apply an external full-scale current on all gain
ranges, apply a lower current and then scale the result produced
by the calibration. For example, apply a 50% current, and then
divide the resulting ADC0GN value by 2 and write this value back
into ADC0GN. Note that there is a lower limit for the input signal
that can be applied during a system calibration because
ADC0GN is only a 16-bit register. The input span (that is, the
difference between the system zero-scale value and the system
full-scale value) should be greater than 40% of the nominal full-
scale-input range (that is, >40% of VREF/gain).
The on-chip Flash/EE memory can be used to store multiple
calibration coefficients. These calibration coefficients can be copied
directly into the relevant calibration registers by user code and
are based on the system configuration. In general, the simplest
way to use the calibration registers is to let the ADC calculate the
values required as part of the ADC automatic calibration modes.
A factory-programmed or end-of-line calibration for the I-ADC
is a two-step procedure.
1.
Apply 0 A current. Configure the ADC in the required PGA
setting, and write to ADCMDE[2:0] to perform a system
zero-scale calibration. This writes a new offset calibration
value into ADC0OF.
2.
Apply a full-scale current for the selected PGA setting. Write
to ADCMDE to perform a system full-scale calibration. This
writes a new gain calibration value into ADC0GN.
Understanding the Offset and Gain Calibration Registers
The output of a typical block in the ADC signal flow (described
in the ADC Sinc3 Digital Filter Response section through the
Using the Offset and Gain Calibration section) can be consid-
ered a fractional number with a span for a ±full-scale input of
approximately ±0.75. The span is less than ±1 because there is
attenuation in the modulator to accommodate some overrange
capacity on the input signal. The exact value of the attenuation
varies slightly from part to part because of manufacturing
tolerances.
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