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| 型號(hào)： | EVAL-ADUC7036QSPZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 48/132頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR ADUC7036 |
| 設(shè)計(jì)資源： | EVAL-ADUC7036 Schematic & Brd Outline EVAL ADUC7036 Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuickStart™ PLUS 套件 |
| 主要目的： | 電源管理，電池監(jiān)控器 |
| 嵌入式： | 是，MCU，16/32 位 |
| 已用 IC / 零件： | ADuC7036 |
| 已供物品： | 板，線纜，文檔，仿真器，電源，軟件 |
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ADuC7036
Rev. C | Page 22 of 132
The minimum latency for FIQ or IRQ interrupts is five cycles.
This consists of the shortest time the request can take through
the synchronizer plus the time to enter the exception mode.
Note that the ARM7TDMI initially (first instruction) runs in
ARM (32-bit) mode when an exception occurs. The user can
immediately switch from ARM mode to Thumb mode if
required, for example, when executing interrupt service routines.
MEMORY ORGANIZATION
The ARM7 MCU core, which has a von Neumann-based
architecture, sees memory as a linear array of 232 byte locations.
As shown in Figure 13, the ADuC7036 maps this into four
distinct user areas: a memory area that can be remapped, an
SRAM area, a Flash/EE area, and a memory mapped register
(MMR) area.
The first 94 kB of this memory space is used as an area into
which the on-chip Flash/EE or SRAM can be remapped.
The ADuC7036 features a second 4 kB area at the top of
the memory map used to locate the MMRs, through which
all on-chip peripherals are configured and monitored.
The ADuC7036 features an SRAM size of 6 kB.
The ADuC7036 features 96 kB of on-chip Flash/EE memory,
94 kB of which are available to the user and 2 kB of which
are reserved for the on-chip kernel.
Any access, either a read or a write, to an area not defined in the
memory map results in a data abort exception.
Memory Format
The ADuC7036 memory organization is configured in little
endian format: the least significant byte is located in the lowest
byte address and the most significant byte in the highest byte
address.
BIT 31
BYTE 2
A
6
2
.
BYTE 3
B
7
3
.
BYTE 1
9
5
1
.
BYTE 0
8
4
0
.
BIT 0
32 BITS
0xFFFFFFFF
0x00000004
0x00000000
0
747
4-
0
12
Figure 12. Little Endian Format
0x00417FF
0x00040000
0xFFFF0FFF
0xFFFF0000
MMRs
0x00097FFF
0x00080000
FLASH/EE
SRAM
0x0017FFF
0x00000000
REMAPPABLE MEMORY SPACE
(FLASH/EE OR SRAM)
RESERVED
0
74
-01
3
Figure 13. Memory Map
SRAM
The ADuC7036 features 6 kB of SRAM, organized as
1536 × 32 bits, that is, 1536 words located at 0x00040000.
The RAM space can be used as data memory and also as a volatile
program space.
ARM code can run directly from SRAM at full clock speed
because the SRAM array is configured as a 32-bit-wide memory
array. SRAM is readable/writeable in 8-, 16-, and 32-bit segments.
Remap
The ARM exception vectors are situated at the bottom of the
memory array, from Address 0x00000000 to Address 0x00000020.
By default, after a reset, the Flash/EE memory is logically
mapped to Address 0x00000000.
It is possible to logically remap the SRAM to Address 0x00000000.
This is accomplished by setting Bit 0 of the SYSMAP0 MMR
located at 0xFFFF0220. To revert Flash/EE to 0x00000000, Bit 0
of SYSMAP0 is cleared.
It may be desirable to remap RAM to 0x00000000 to optimize the
interrupt latency of the ADuC7036 because code can run in full
32-bit ARM mode and at maximum core speed. It should be noted
that when an exception occurs, the core defaults to ARM mode.
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